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Piranha: a scalable architecture based on single-chip multiprocessing
This paper describes the Piranha system, a research prototype being developed at Compaq that aggressively exploits chip multiprocessing by integrating eight simple Alpha processor cores along with aExpand
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Fingerprinting: bounding soft-error-detection latency and bandwidth
Recent studies suggest that the soft-error rate in microprocessor logic is likely to become a serious reliability concern by 2010. Detecting soft errors in the processor's core logic presents a newExpand
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PHAST: Hardware-Accelerated Shortest Path Trees
We present a novel algorithm to solve the nonnegative single-source shortest path problem on road networks and other graphs with low highway dimension. After a quick preprocessing phase, we canExpand
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Missing the Memory Wall: The Case for Processor/Memory Integration
Current high performance computer systems use complex, large superscalar CPUs that interface to the main memory through a hierarchy of caches and interconnect systems. These CPU-centric designsExpand
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SimFlex: a fast, accurate, flexible full-system simulation framework for performance evaluation of server architecture
The new focus on commercial workloads in simulation studies of server systems has caused a drastic increase in the complexity and decrease in the speed of simulation tools. The complexity of aExpand
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Formal specification of abstract memory models
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PHAST: Hardware-accelerated shortest path trees
Abstract We present a novel algorithm to solve the non-negative single-source shortest path problem on road networks and graphs with low highway dimension. After a quick preprocessing phase, we canExpand
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Implementing simple coma on s3-mp
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The S3.mp scalable shared memory multiprocessor
S3.mp (Sun's Scalable Shared memory MultiProcessor) is a research project to demonstrate a low overhead, high throughput communication system that is based on cache coherent distributed shared memoryExpand
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