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An Analyzable Memory Controller for Hard Real-Time CMPs
TLDR
An analyzable JEDEC-compliant DDRx SDRAM memory controller (AMC) for hard real-time CMPs is proposed, that reduces the impact of memory interferences caused by other tasks on WCET estimation, providing a predictable memory access time and allowing the computation of tight WCET estimations.
View on IEEE
The International Exascale Software Project roadmap
TLDR
The work of the community to prepare for the challenges of exascale computing is described, ultimately combing their efforts in a coordinated International Exascale Software Project.
View on SAGE
Dynamically Controlled Resource Allocation in SMT Processors
TLDR
This paper proposes a novel resource allocation policy for SMT processors that directly monitors the usage of resources by each thread and guarantees that all threads get their fair share of the critical shared resources, avoiding monopolization.
View on ACM
Multiple-banked register file architectures
TLDR
This paper proposes a register file architecture composed of multiple banks, which provides low latency and simple bypass logic and shows that a two-level organization degrades IPC and increases performance by 87% and 92% when the register file access time is factored in.
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Enabling preemptive multiprogramming on GPUs
TLDR
This paper argues for preemptive multitasking and design two preemption mechanisms that can be used to implement GPU scheduling policies and extends the NVIDIA GK110 (Kepler) like GPU architecture to allow concurrent execution of GPU kernels from different user processes and implements a scheduling policy that dynamically distributes the GPU cores among concurrently running kernels, according to their priorities.
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Hardware support for WCET analysis of hard real-time multicore systems
TLDR
This paper proposes a multicore architecture with shared resources that allows the execution of applications with hard real-time and non hardreal-time constraints at the same time, providing time analizability for the hard Real-time tasks so that they can meet their deadlines.
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Swing module scheduling: a lifetime-sensitive approach
TLDR
This paper presents a novel software pipelining approach, which is called Swing Modulo Scheduling (SMS), that generates schedules that are near optimal in terms of initiation interval, register requirements and stage count and is compared with other heuristic methods showing that it outperforms them interms of the quality of the obtained schedules and compilation time.
View on IEEE
Supercomputing with commodity CPUs: Are mobile SoCs ready for HPC?
TLDR
The trend in mobile SoC performance is analyzed, comparing it with the similar trend in the 1990s, and a first answer as to whether mobile SoCs are ready for HPC is given.
View on ACM
Criticality-Aware Dynamic Task Scheduling for Heterogeneous Architectures
TLDR
The OmpSs approach on scheduling dependent tasks onto the asymmetric cores of a heterogeneous system improves performance by prioritizing the newly-created tasks at runtime, detecting the longest path of the dynamic task dependency graph, and assigning critical tasks to fast cores.
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Parallel Computer Architecture
Computer architecture is a truly fascinating field in tha improvements in the basic echnology and innovations how to make best use of he underlying tech- nology has yielded a performance growth…
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