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Dynamic random-access memory
Known as:
Synchronous graphics RAM
, Dynamic Random access memory
, BEDO (RAM)
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Dynamic random-access memory (DRAM) is a type of random-access memory that stores each bit of data in a separate capacitor within an integrated…
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Apple Watch
Application-specific integrated circuit
CPU cache
Cold boot attack
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Papers overview
Semantic Scholar uses AI to extract papers important to this topic.
Review
2014
Review
2014
Three dimensional dynamic random access memory
T. Kirihata
4th IEEE International Workshop on Low…
2014
Corpus ID: 30603112
We review high-density embedded 3D DRAM cache, industry 3D stacked DDR3 and wide IO mobile DRAM along with more recent Hybrid…
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Highly Cited
2013
Highly Cited
2013
Worst Case Analysis of DRAM Latency in Multi-requestor Systems
Z. Wu
,
Yogen Krish
,
R. Pellizzoni
IEEE Real-Time Systems Symposium
2013
Corpus ID: 20299227
As multi-core systems are becoming more popular in real-time embedded systems, strict timing requirements for accessing shared…
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2012
2012
Dynamic random-access memories without sense amplifiers
S. Sharroush
,
Y. Abdalla
,
A. Dessouki
,
E. El-Badawy
Elektrotech. Informationstechnik
2012
Corpus ID: 13286329
ZusammenfassungWährend des Leseprozesses von dynamischen Ein-Transistor-/Ein-Kondensator-DRAM-Speicherzellen (1T-1C DRAM) ist es…
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2010
2010
Dynamic random access memory (dram) refresh
ペレイ,ペリー,エイチ,サード
,
ホークストラ,ジョージ,ピー
2010
Corpus ID: 108335599
A method for refreshing a Dynamic Random Access Memory (DRAM) includes performing a refresh on at least a portion of the DRAM at…
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Review
2003
Review
2003
Embedded dynamic random access memory
T. Kirihata
International Symposium on VLSI Technology…
2003
Corpus ID: 53778549
For several decades, the 1-transistor Dynamic Random Access Memory (DRAM) has been the dominant choice for high density and low…
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Review
1999
Review
1999
Dynamic Random Access Memory: A Survey
T. Mitra
1999
Corpus ID: 18354331
The increasing gap between processor speed and main memory latency has accelerated the development of various innovative…
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Highly Cited
1999
Highly Cited
1999
A Programmable BIST Core for Embedded DRAM
Chih-Tsun Huang
,
Jing-Reng Huang
,
Chi-Feng Wu
,
Cheng-Wen Wu
,
Tsin-Yuan Chang
IEEE Design & Test of Computers
1999
Corpus ID: 28276441
The programmable BIST design presented here supports various test modes using a simple controller. With the March C algorithm…
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1994
1994
A proposed SEU tolerant dynamic random access memory (DRAM) cell
G. Agrawal
,
L. Massengill
,
K. Gulati
1994
Corpus ID: 14776249
A novel DRAM cell technology consisting of an n-channel access transistor and a bootstrapped storage capacitor with an integrated…
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1986
1986
Neutron Dosimeter Using a Dynamic Random Access Memory as a Sensor
J. Lund
,
F. Sinclair
,
G. Entine
IEEE Transactions on Nuclear Science
1986
Corpus ID: 7375805
Soft errors in memory devices caused by ionizing radiation are well known. This sensitivity means that dynamic random access…
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1973
1973
A 4K MOS dynamic random-access memory
R. Abbott
,
W. Regitz
,
J. Karp
1973
Corpus ID: 62629468
Presents one version of a 4K dynamic MOS random-access memory utilizing a 3 device/bit cell with an area of less than 2 mil/SUP 2…
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