Skip to search formSkip to main contentSkip to account menu

Dynamic random-access memory

Known as: Synchronous graphics RAM, Dynamic Random access memory, BEDO (RAM) 
Dynamic random-access memory (DRAM) is a type of random-access memory that stores each bit of data in a separate capacitor within an integrated… 
Wikipedia (opens in a new tab)

Related topics

Related topics

49 relations
Apple WatchApplication-specific integrated circuitCPU cacheCold boot attack

Papers overview

Semantic Scholar uses AI to extract papers important to this topic.
2013
2013
An Edo Anthology
During the eighteenth century, Edo (today's Tokyo) became the world's largest city, quickly surpassing London and Paris. Its… 
2010
2010
Dynamic random access memory (dram) refresh
A method for refreshing a Dynamic Random Access Memory (DRAM) includes performing a refresh on at least a portion of the DRAM at… 
Highly Cited
2003
Highly Cited
2003
Schema-guided wrapper maintenance for web-data extraction
Extracting data from Web pages using wrappers is a fundamental problem arising in a large variety of applications of vast… 
2002
2002
Dynamic random access memory system with bank conflict avoidance feature
PURPOSE: A memory system, a processing system, a using method of the memory system, are provided to be capable of preventing bank… 
Highly Cited
2001
Highly Cited
2001
High-performance and low-power memory-interface architecture for video processing applications
To improve memory bandwidth and power consumption in video applications, a new memory-interface architecture is proposed. The… 
2000
2000
Virtual channel synchronous dynamic random access memory
PURPOSE: To provide a VCM semiconductor memory. CONSTITUTION: By reducing what is controlled by one line of Main Word in a WDRV… 
Highly Cited
1998
Highly Cited
1998
A precise on-chip voltage generator for a giga-scale DRAM with a negative word-line scheme
We have designed a precise on-chip voltage generator for giga-scale DRAMs with a negative word-line scheme. It combines a charge… 
1987
1987
Selector-line merged built-in ECC technique for DRAMs
A high-performance built-in error checking and correcting (ECC) technique applicable to megabit-level dynamic RAM (DRAM) chips is… 
1980
1980
An 18K bipolar dynamic random access memory
A 2K/spl times/9 bipolar dynamic random access memory (RAM) experimental chip is described with a 75 ns and 300 ns access and… 
1973
1973
A 4K MOS dynamic random-access memory
Presents one version of a 4K dynamic MOS random-access memory utilizing a 3 device/bit cell with an area of less than 2 mil/SUP 2… 
By clicking accept or continuing to use the site, you agree to the terms outlined in our Privacy Policy (opens in a new tab), Terms of Service (opens in a new tab), and Dataset License (opens in a new tab)