• Publications
  • Influence
A 500 MHz Random Cycle, 1.5 ns Latency, SOI Embedded DRAM Macro Featuring a Three-Transistor Micro Sense Amplifier
TLDR
This paper describes a 500 MHz random cycle silicon on insulator embedded DRAM macro which features a three-transistor micro sense amplifier, realizing significant performance gains over traditional array design methods. Expand
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A 45 nm SOI Embedded DRAM Macro for the POWER™ Processor 32 MByte On-Chip L3 Cache
TLDR
A 1.35 ns random access and 1.7 ns random-cycle embedded-DRAM macro has been developed for the POWER7™ high-performance microprocessor. Expand
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An 800-MHz embedded DRAM with a concurrent refresh mode
TLDR
An 800-MHz embedded DRAM macro employs a memory cell utilizing a device from the 90-nm high-performance technology menu; a 2.2-nm gate oxide 1.5 V IO device. Expand
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A 500MHz Random Cycle 1.5ns-Latency, SOI Embedded DRAM Macro Featuring a 3T Micro Sense Amplifier
  • J. Barth, W. Reohr, +14 authors S. Iyer
  • Engineering, Computer Science
  • IEEE International Solid-State Circuits…
  • 18 June 2007
TLDR
A prototype SOI embedded DRAM macro is developed for high-performance microprocessors and introduces performance-enhancing 3T micro sense amplifier architecture (muSA). Expand
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Electrically Programmable Fuse (eFUSE): From Memory Redundancy to Autonomic Chips
  • N. Robson, J. Safran, +7 authors S. Iyer
  • Engineering, Computer Science
  • IEEE Custom Integrated Circuits Conference
  • 1 September 2007
TLDR
We will review the evolution and applications of electrical fuse solutions for 180 nm to 45 nm technologies at IBM, and provide some insight into future uses in 32 nm technology and beyond. Expand
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Field Tolerant Dynamic Intrinsic Chip ID Using 32 nm High-K/Metal Gate SOI Embedded DRAM
TLDR
A random intrinsic chip ID generation method using retention fails is implemented in 32 nm SOI embedded DRAM. Expand
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Fault-tolerant designs for 256 Mb DRAM
TLDR
This paper describes fault-tolerant designs, which have been used to boost the yield of a 286 mm/sup 2/ 256 Mb DRAM with x32 both-ends DQ. Expand
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A 0.039um2 high performance eDRAM cell based on 32nm High-K/Metal SOI technology
We present industry's smallest eDRAM cell and the densest embedded memory integrated into the highest performance 32nm High-K Metal Gate (HKMG) SOI based logic technology. The cell is aggressivelyExpand
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A 0.127 μm2 High Performance 65nm SOI Based embedded DRAM for on-Processor Applications
The authors present a 65nm embedded DRAM cell (0.127 μm2 cell size) on unpatterned SOI fabricated using standard high performance SOI technology with dual stress liner (DSL). The cell utilizes aExpand
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A 2.9ns random access cycle embedded DRAM with a destructive-read
TLDR
A destructive-read architecture that reduces the random access cycle time of an eDRAM by delaying the data write back operation to a later cycle is demonstrated. Expand
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