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A genetic algorithm for task scheduling on heterogeneous computing systems using multiple priority queues
TLDR
A heuristic-based task scheduling algorithm on heterogeneous computing systems using a multiple priority queues genetic algorithm (MPQGA) is proposed. Expand
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Stream Bench: Towards Benchmarking Modern Distributed Stream Computing Frameworks
TLDR
This paper takes an early step towards benchmarking modern distributed stream computing frameworks. Expand
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Reprogramming with Minimal Transferred Data on Wireless Sensor Network
  • J. Hu, C. Xue, Yi He, E. Sha
  • Computer Science
  • IEEE 6th International Conference on Mobile Adhoc…
  • 17 November 2009
TLDR
We propose an algorithm, Reprogramming with Minimal Transferred Data (RMTD), to find the optimum combination of copying from the old code image and downloading from the host machine to minimize the number of bytes needed to be transferred from thehost machine to a sensor node. Expand
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Two-step state transition minimization for lifetime and performance improvement on MLC STT-RAM
TLDR
This paper proposes a novel two-step state transition minimization (TSTM) scheme, to improve the lifetime of MLC STT-RAM when it is employed in cache design. Expand
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Energy-aware preemptive scheduling algorithm for sporadic tasks on DVS platform
TLDR
We propose a novel energy-aware scheduling algorithm named Cycle Conserve Dynamic Voltage Scaling for Sporadic Tasks (CC-DVSST) algorithm which is an improvement to DVSST. Expand
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Towards energy efficient hybrid on-chip Scratch Pad Memory with non-volatile memory
TLDR
We propose a novel hybrid SPM which consists of non-volatile memory (NVM) and SRAM to take advantage of the low leakage power consumption and high density of NVM as well as the efficient writes of SRAM. Expand
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Routing path reuse maximization for efficient NV-FPGA reconfiguration
TLDR
This paper proposes a routing path reuse technique to efficiently configure switch boxes, the majority component of an FPGA, which is able to achieve as much as 40% path reuse rate and reduce configuration cost. Expand
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Accuracy vs. Efficiency: Achieving Both through FPGA-Implementation Aware Neural Architecture Search
TLDR
We use Field Programmable Gate Arrays (FPGAs) as a vehicle to present a novel hardware-aware NAS framework, namely FNAS, which will provide an optimal neural architecture with latency guaranteed to meet the specification. Expand
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Checkpoint aware hybrid cache architecture for NV processor in energy harvesting powered systems
TLDR
We propose replacement and checkpoint policies for SRAM and NVM based hybrid cache in NVPs whose execution is interrupted frequently. Expand
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DAC-SDC Low Power Object Detection Challenge for UAV Applications
  • X. Xu, X. Zhang, +4 authors Y. Shi
  • Computer Science, Medicine
  • IEEE transactions on pattern analysis and machine…
  • 1 September 2018
TLDR
The 55th Design Automation Conference (DAC) held its first System Design Contest (SDC) in 2018. Expand
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