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Scaling to the end of silicon with EDGE architectures
The TRIPS architecture is the first instantiation of an EDGE instruction set, a new, post-RISC class of instruction set architectures intended to match semiconductor technology evolution over the next decade, scaling to new levels of power efficiency and high performance.
A novel low power energy recovery full adder cell
The proposed SERF adder design was proven to be superior to the other three designs in power dissipation and area, and second in propagation delay only to the DVL adder.
Complete System Power Estimation: A Trickle-Down Approach Based on Performance Events
This paper is the first to create power models for the entire system based on processor performance events and shows how well known performance-related events within a microprocessor such as cache misses and DMA transactions are highly correlated to power consumption outside of the microprocessor.
Complete System Power Estimation Using Processor Performance Events
Using measurement of actual systems running scientific, commercial and productivity workloads, power models for six subsystems on two platforms are developed and validated and it is possible to estimate system power consumption without the need for power sensing hardware.
Run-time modeling and estimation of operating system power consumption
The most striking observation is the strong correlation between power consumption and the instructions per cycle (IPC) during OS routine executions, and the proposed models can estimate OS power for run-time dynamic thermal and energy management.
Analysis of redundancy and application balance in the SPEC CPU2006 benchmark suite
This paper analyzes the SPEC CPU2006 benchmarks using performance counter based experimentation from several state of the art systems, and uses statistical techniques such as principal component analysis and clustering to draw inferences on the similarity of the benchmarks and the redundancy in the suite and arrive at meaningful subsets.
Digital Systems Design Using VHDL
This book emphasizes the practical use of VHDL in the digital design process and introduces methods for testing digital systems including boundary scan and a built-in self-test.
Elastic Refresh: Techniques to Mitigate Refresh Penalties in High Density Memory
- Jeffrey Stuecheli, Dimitris Kaseridis, H. Hunter, L. John
- Computer Science43rd Annual IEEE/ACM International Symposium on…
- 4 December 2010
This work proposes dynamically reconfigurable predictive mechanisms that exploit the full dynamic range allowed in the JEDEC DDRx SDRAM specifications, and refers to the overall scheme as Elastic Refresh, in that the refresh policy is stretched to fit the currently executing workload, such that the maximum benefit of the DRAM flexibility is realized.
The virtual write queue: coordinating DRAM and last-level cache policies
This paper demonstrates that performance limiting effects of highly-threaded architectures can be overcome, and shows that through awareness of the physical main memory layout and by focusing on writes, both read and write average latency can be shortened, memory power reduced, and overall system performance improved.
Efficient program scheduling for heterogeneous multi-core processors
The proposed method projects the core's configuration and the program's resource demand to a unified multi-dimensional space, and uses weighted Euclidean distance between these two to guide the program scheduling.