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Bit-level parallelism

Known as: Bitlevel parallelisms, Bit-level devices, Bit levels 
Bit-level parallelism is a form of parallel computing based on increasing processor word size. From the advent of very-large-scale integration (VLSI… 
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Related topics

Related topics

14 relations
16-bit32-bit4-bit8-bit

Broader (1)

Parallel computing

Papers overview

Semantic Scholar uses AI to extract papers important to this topic.
2011
2011
A Novel Chaos-based Image Encryption Scheme with an Improved Permutation Process
Confidentiality is an important issue when digital images are transmitted over public networks, and encryption is the most useful… 
2009
2009
On Providing Intelligibility-Aware Preservation Services for Digital Objects
Preserving digital objects requires preservation of not only their bit-level representation but also their intelligibility. To… 
2008
2008
A High-Speed Viterbi Decoder
Convolutional codes are widely used in many communication systems due to their excellent error-control performance. High-speed… 
2000
2000
Design and FPGA implementation of orthonormal discrete wavelet transforms
FPGA technology offers the potential for low cost and high performance for certain applications, including image processing… 
1999
1999
Arithmetic circuits for analog digits
The Overlap Resolution Number System (ORNS) employs bit level analog residue arithmetic, and opens up a powerful approach to… 
1997
1997
A VLSI design methodology for RNS full adder-based inner product architectures
In this paper, a systematic graph-based methodology for synthesizing VLSI RNS architectures using full adders as the basic… 
1996
1996
VLSI Implementation of a Selective Median Filter
0001 0 0 1 0 0011 0111 1001 In this paper, the VLSI implementation of a selective median filter for the real-time applications is… 
1991
1991
Bit-level pipelined 2-D digital filters for real-time image processing
  • Cheng-Wen Wu
  • IEEE Trans. Circuits Syst. Video Technol.
  • 1991
  • Corpus ID: 11268295
Bit-level systolic arrays for real-time 2-D FIR and IIR (finite and infinite impulse response) filters are presented. Two… 
1989
1989
Bit-Level systolic architectures for high performance IIR filtering
Several novel systolic architectures for implementing densely pipelined bit parallel IIR filter sections are presented. The… 
Highly Cited
1982
Highly Cited
1982
Completely iterative, pipelined multiplier array suitable for VLSI
A pipelined array multiplier which has been derived by applying 'systolic array' principles at the bit level is described…