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Bit-level parallelism

Known as: Bitlevel parallelisms, Bit-level devices, Bit levels 
Bit-level parallelism is a form of parallel computing based on increasing processor word size. From the advent of very-large-scale integration (VLSI… 
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Related topics

Related topics

14 relations
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Broader (1)

Parallel computing

Papers overview

Semantic Scholar uses AI to extract papers important to this topic.
Highly Cited
2011
Highly Cited
2011
A frequent-value based PRAM memory architecture
Phase Change Random Access Memory (PRAM) has great potential as the replacement of DRAM as main memory, due to its advantages of… 
Highly Cited
2009
Highly Cited
2009
Focal-Plane Algorithmically-Multiplying CMOS Computational Image Sensor
The CMOS image sensor computes two-dimensional convolution of video frames with a programmable digital kernel of up to 8 times 8… 
Highly Cited
2005
Highly Cited
2005
Platform-based design from parallel C specifications
This paper presents Disydent, a framework dedicated to system-on-a-chip (SoC) platform-based design for shared memory multiple… 
Highly Cited
2002
Highly Cited
2002
Bluetooth and IEEE 802.11 coexistence: analytical performance evaluation in fading channel
The performance in terms of the mean packet error probability (PEP) in a Rayleigh fading channel with thermal noise is… 
Highly Cited
2000
Highly Cited
2000
A multiple input-multiple output channel model for simulation of Tx- and Rx-diversity wireless systems
Space-time receivers for wireless communication systems offer the possibility to have both Tx- and Rx-antennas. For a realistic… 
Highly Cited
2000
Highly Cited
2000
A simple processor core design for DCT/IDCT
This paper presents a cost-effective processor core design that features the simplest hardware and is suitable for discrete… 
Highly Cited
1997
Highly Cited
1997
VLSI array algorithms and architectures for RSA modular multiplication
  • Y. JeongW. Burleson
  • IEEE Transactions on Very Large Scale Integration…
  • 1997
  • Corpus ID: 36721067
We present two novel iterative algorithms and their array structures for integer modular multiplication. The algorithms are… 
1996
1996
VLSI Implementation of a Selective Median Filter
0001 0 0 1 0 0011 0111 1001 In this paper, the VLSI implementation of a selective median filter for the real-time applications is… 
Highly Cited
1987
Highly Cited
1987
Parallel bit-level pipelined VLSI designs for high-speed signal processing
This paper explores the potential of bit-level pipelined VLSI for high-speed signal processing. We discuss issues involved in… 
Highly Cited
1982
Highly Cited
1982
Completely iterative, pipelined multiplier array suitable for VLSI
A pipelined array multiplier which has been derived by applying 'systolic array' principles at the bit level is described… 
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