• Publications
  • Influence
A novel architecture of the 3D stacked MRAM L2 cache for CMPs
TLDR
We first stackMRAM-based L2 caches directly atop CMPs and compare it against SRAM counterparts in terms of performance and energy. Expand
  • 416
  • 42
  • PDF
Circuit and microarchitecture evaluation of 3D stacking magnetic RAM (MRAM) as a universal memory replacement
TLDR
We discuss the circuit design issues for MRAM, and present the MRAM cache model. Expand
  • 313
  • 21
  • PDF
Energy-efficient multi-level cell phase-change memory system with data encoding
TLDR
We propose an energy-efficient PCM architecture using data encoding write based on the observation that there are significant value-dependent energy variations in programming MLC PCM. Expand
  • 58
  • 15
  • PDF
Adaptive placement and migration policy for an STT-RAM-based hybrid cache
TLDR
We propose an adaptive block placement and migration policy (APM) for hybrid caches that places a block into either STT-RAM lines or SRAM lines by adapting to the access pattern of each class. Expand
  • 95
  • 13
  • PDF
Hi-fi playback: Tolerating position errors in shift operations of racetrack memory
TLDR
Racetrack memory is an emerging non-volatile memory based on spintronic domain wall technology. Expand
  • 44
  • 11
  • PDF
An efficient design and implementation of LSM-tree based key-value store on open-channel SSD
TLDR
We propose LOCS, a system equipped with a customized SSD design, which exposes its internal flash channels to applications, to work with the LSM-tree-based KV store, specifically LevelDB in this work. Expand
  • 106
  • 9
  • PDF
Energy- and endurance-aware design of phase change memory caches
TLDR
We study a set of techniques to design an energy- and endurance-aware PCM cache that can achieve 8% of energy saving and 3.8 years of lifetime compared with baseline PCM caches. Expand
  • 129
  • 8
  • PDF
Architecting on-chip interconnects for stacked 3D STT-RAM caches in CMPs
TLDR
In this paper, we study the integration of STT-RAM in a 3D multi-core environment and propose solutions at the on-chip network level to circumvent the write overhead problem in the cache architecture with STt-RAM technology. Expand
  • 95
  • 8
  • PDF
Half-DRAM: A high-bandwidth and low-power DRAM architecture from the rethinking of fine-grained activation
TLDR
We propose a novel memory architecture Half-DRAM, in which the DRAM array is reorganized to enable only half of a row being activated. Expand
  • 86
  • 8
  • PDF
Fork Path: Improving efficiency of ORAM by removing redundant memory accesses
  • X. Zhang, Guangyu Sun, +5 authors J. Di
  • Computer Science
  • 48th Annual IEEE/ACM International Symposium on…
  • 5 December 2015
TLDR
Oblivious RAM (ORAM) is a cryptographic primitive that can prevent information leakage in the access trace to untrusted external memory. Expand
  • 27
  • 7
  • PDF