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16-bit
Known as:
16 bit application
, 64k barrier
, 16-bit architecture
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In computer architecture, 16-bit integers, memory addresses, or other data units are those that are at most 16 bits (2 octets) wide. Also, 16-bit CPU…
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Related topics
Related topics
50 relations
32-bit
86-DOS
AVR32
Apollo Guidance Computer
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Papers overview
Semantic Scholar uses AI to extract papers important to this topic.
2013
2013
RTOS Based Priority Dynamic Scheduling for Power Applications through DMA Peripherals
Narayanaraju Samunuri
2013
Corpus ID: 212500656
--Embedded Real Time application uses multi threading, a key concept of any conventional OS. The advantage of multi-threading…
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2013
2013
Randomized methods in lossless compression of hyperspectral data
Qiang Zhang
,
V. Pauca
,
R. Plemmons
2013
Corpus ID: 15846823
Abstract We evaluate recently developed randomized matrix decomposition methods for fast lossless compression and reconstruction…
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Highly Cited
2010
Highly Cited
2010
Design of High-speed Modified Booth Multipliers Operating at GHz Ranges
Soojin Kim
,
Kyeongsoon Cho
2010
Corpus ID: 17071803
— This paper describes the pipeline architecture of high-speed modified Booth multipliers. The proposed multiplier circuits are…
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2010
2010
Generic and Orthogonal March Element based Memory BIST Engine
S. H. Kukner
2010
Corpus ID: 107918773
A Memory BIST architecture and implementation based on the novel concept of Generic and Orthogonal March Element
2007
2007
Ultrafast All-Optical Serial-to-Parallel Converters Based on Spin-Polarized Surface-Normal Optical Switches
R. Takahashi
,
T. Yasui
,
Jae-Kuk Seo
,
H. Suzuki
IEEE Journal of Selected Topics in Quantum…
2007
Corpus ID: 20782398
We describe our recent work on all-optical serial-to-parallel converters (SPCs), from the all-optical switches employed in the…
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2006
2006
Store Vulnerability Window (SVW): A Filter and Potential Replacement for Load Re-Execution
A. Roth
J. Instr. Level Parallelism
2006
Corpus ID: 16341191
Load scheduling and execution are performance critical aspects of dynamically-scheduled processing. Several techniques employ…
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2005
2005
Matrix Converter Control System
J. Lettl
,
S. Fligl
2005
Corpus ID: 55804223
The presented paper deals with the matrix converter control hardware and software conception. The built matrix converter is used…
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2003
2003
Dissecting a C# Application: Inside SharpDevelop
C. Holm
,
Bernhard Spuida
,
M. Kruger
2003
Corpus ID: 62089417
From the Publisher: Learn advanced .NET programming techniques by getting an insiders' look at a complete application…
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2001
2001
Optimal Datapath Design for a Cryptographic Processor: The Blowfish Algorithm
N. B. Z. Ali
,
J. Noras
2001
Corpus ID: 62647396
BLOWFISH is a fast cryptographic software algorithm, using the operations of addition, XOR and look-up tables. This paper reports…
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1998
1998
Faster learning of control parameters through sharing experiences of autonomous mobile robots
I. Kelly
,
D. Keating
International Journal of Systems Science
1998
Corpus ID: 1088130
This paper describes a learning algorithm for small autonomous mobile robots based on sets of fuzzy automata. The task of the…
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