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Modified Montgomery modular multiplication and RSA exponentiation techniques
Modified Montgomery multiplication and associated RSA modular exponentiation algorithms and circuit architectures are presented. These modified multipliers use carry save adders (CSAs) to perform
A VLSI architecture for variable block size video motion estimation
  • S. Y. Yap, J. McCanny
  • Computer Science
    IEEE Transactions on Circuits and Systems II…
  • 19 July 2004
TLDR
A new one-dimensional (1-D) very large-scale integration architecture for full-search VBSME (FSVBSME), which can process up to 41 MV sub-blocks (within a macroblock) in the same number of clock cycles.
Fast Montgomery modular multiplication and RSA cryptographic processor architectures
TLDR
New, generic silicon architectures for implementing Montgomery's multiplication algorithm are presented and it is shown that using a four-to-two CSA with two extra registers rather than a five- to- two CSA leads to a useful reduction in the critical path of the multiplier, albeit at the expense of a small increase in circuitry.
High Performance Single-Chip FPGA Rijndael Algorithm Implementations
TLDR
High performance single-chip FPGA implementations of the new Advanced Encryption Standard (AES) algorithm, Rijndael are described, with a novel, generic, parameterisable RIJndael encryptor core capable of supporting varying key sizes.
Rijndael FPGA implementation utilizing look-up tables
  • W. McLoone, J. McCanny
  • Computer Science
    IEEE Workshop on Signal Processing Systems. SiPS…
  • 26 September 2001
TLDR
An FPGA Rijndael encryption design is presented, which utilizes look-up tables to implement the entire RIJndael Round function, which achieves a speed of 12 Gbits/sec, which is a factor 1.2 times faster than an alternative design.
High-performance FPGA implementation of DES using a novel method for implementing the key schedule
TLDR
A generic, parameterisable key scheduling core is presented, which can be utilised in pipelinable private-key encryption algorithms and the broader applicability of the method to other encryption algorithms is illustrated.
A VLSI architecture for advanced video coding motion estimation
  • S. Y. Yap, J. McCanny
  • Computer Science
    Proceedings IEEE International Conference on…
  • 24 June 2003
TLDR
This work proposes a new 1-D VLSI architecture for full search variable block size motion estimation (FSVBSME), which can process up to 41 motion vector subblocks (within a macroblock) in a comparable number of clock cycles.
Hardware Elliptic Curve Cryptographic Processor Over$rm GF(p)$
TLDR
A novel hardware architecture for elliptic curve cryptography (ECC) over GF(p) is introduced, based on a new unified modular inversion algorithm that offers considerable improvement over previous ECC techniques that use Fermat's Little Theorem for this operation.
Efficient single-chip implementation of SHA-384 and SHA-512
TLDR
A novel highly efficient single-chip hardware design of the SHA-384 and SHA-512 authentication algorithms achieves a throughput of 479 Mbits/sec utilising a shift register design approach and look-up tables (LUTs).
High-radix systolic modular multiplication on reconfigurable hardware
TLDR
Novel high radix systolic array Montgomery multiplier designs are presented, as it is believed that the inherent regular structure and absence of global interconnect associated with these, make them well-suited for implementation on modern FPGAs.
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