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VLSI Test Principles and Architectures: Design for Testability (Systems on Silicon)
This book is a comprehensive guide to new DFT methods that will show the readers how to design a testable and quality product, drive down test cost, improve product quality and yield, and speed upExpand
Built-in redundancy analysis for memory yield improvement
TLDR
Three redundancy analysis algorithms which can be implemented on-chip based on the local-bitmap idea are presented: the local repair-most approach is efficient for a general spare architecture, and the local optimization approach has the best repair rate. Expand
RRAM Defect Modeling and Failure Analysis Based on March Test and a Novel Squeeze-Search Scheme
TLDR
This paper proposes defect and fault models specific to RRAM, i.e., the Over-Forming (OF) defect and the Read-One-Disturb (R1D) fault, and develops a novel squeeze-search scheme to identify the OF defect, which leads to the Stuck-At Fault (SAF). Expand
On-chip testing of blind and open-sleeve TSVs for 3D IC before bonding
TLDR
This paper presents two schemes for testing through-silicon vias (TSVs) by performing on-chip screening before wafer thinning and bonding, using a charge-sharing technique commonly seen in DRAM and open-sleeve TSVs, respectively. Expand
On-Chip TSV Testing for 3D IC before Bonding Using Sense Amplification
We present a novel testing scheme for TSVs in a 3D IC by performing on-chip TSV monitoring before bonding, using a sense amplification technique that is commonly seen on a DRAM. By virtue of theExpand
March-based RAM diagnosis algorithms for stuck-at and coupling faults
TLDR
March-based RAM diagnosis algorithms which not only locate faulty cells but also identify their types, and can distinguish all of the inter-word and intra- word coupling faults, and locate the coupling cells of the intra-word inversion and idempotent coupling faults. Expand
Testing content-addressable memories using functional fault modelsand march-like algorithms
TLDR
A complete, compact test is proposed, which has low complexity and is suitable for modern high-density and large-capacity CAMs-it requires only 2N+3w+2 compare operations and 8N write operations to cover the functional fault models discussed. Expand
Flash memory built-in self-test using March-like algorithms
TLDR
Improved March-like algorithms are proposed for both bit-oriented and word-oriented flash memory to cover the disturbance faults derived from the IEEE 1005 Standard, as well as conventional faults. Expand
A high-throughput low-cost AES processor
TLDR
An efficient hardware implementation of the advanced encryption standard algorithm, with key expansion capability, with a very high throughput rate, and the proposed basis transformation technique reduces the hardware overhead of the S-box by 64 percent. Expand
RSA cryptosystem design based on the Chinese remainder theorem
TLDR
The design and implementation of a systolic RSA cryptosystem based on a modified Montgomery's algorithm and the Chinese Remainder Theorem technique and the CRT technique is presented, which improves the throughput rate up to 4 times in the best case. Expand
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