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On the data reuse and memory bandwidth analysis for full-search block-matching VLSI architecture
TLDR
This work explores the data reuse properties of full-search block-matching for motion estimation (ME) and associated architecture designs, as well as memory bandwidth requirements, and a seven-type classification system is developed that can accommodate most published ME architectures.
Algorithm and Architecture of Disparity Estimation With Mini-Census Adaptive Support Weight
TLDR
A high-performance hardware-friendly disparity estimation algorithm called mini-census adaptive support weight (MCADSW) is proposed and its corresponding real-time very large scale integration (VLSI) architecture is proposed.
Fast Motion Estimation Algorithm and Design for Real Time QFHD High Efficiency Video Coding
TLDR
A predictive integer ME (IME) algorithm that selects the most probable search directions and steps through a statistical analysis to reduce the number of search points is proposed and an early motion vector prediction candidate approach is proposed.
A Hardware-Efficient H.264/AVC Motion-Estimation Design for High-Definition Video
TLDR
A low-latency and hardware-efficient ME design with three design techniques that adopts parallel instead of serial multiresolution search, and applies a mode-filtering approach to further reduce the bandwidth and cycles and share the buffer of IME and FME.
Real-time high-definition stereo matching on FPGA
TLDR
A real-time high definition stereo matching design on FPGA that is robust to radiometric differences and produces accurate disparity maps by using the Mini-Census transform and the Cross-based cost aggregation.
A 242mW, 10mm2 1080p H.264/AVC high profile encoder chip
A 1080 p high profile H.264 encoder is designed by the robust reusable silicon IP methodology and fabricated in a 0.13 mum CMOS technology with an area of 10 mm2 and 242 mW at 145 MHz. Compared to
Fast SIFT Design for Real-Time Visual Feature Extraction
TLDR
A layer parallel SIFT (LPSIFT) with integral image, and its parallel hardware design with an on-the-fly feature extraction flow for real-time application needs, which reduces the computational amount by 90% and memory usage by 95%.
A 140-MHz 94 K Gates HD1080p 30-Frames/s Intra-Only Profile H.264 Encoder
TLDR
This paper presents a HD1080p 30-frames/s H.264 intra encoder operated at 140 MHz with just 94 K gate count and 0.72-mm2 core area to achieve high throughput and low area cost for high-definition video, and adopts the modified three-step fast intra prediction technique to reduce the cycle count.
A High-Definition H.264/AVC Intra-Frame Codec IP for Digital Video and Still Camera Applications
TLDR
This paper presents a real-time high-definition 720p@30fps H.264/MPEG-4 AVC intra-frame codec IP suitable for digital video and digital still camera applications and proposes to remove the area-costly plane mode, and enhance the cost function to reduce hardware cost and to increase the processing speed while provide nearly the same quality.
A zero-skipping multi-symbol CAVLC decoder for MPEG-4 AVC/H.264
TLDR
A high-performance CAVLC decoding VLSI architecture for MPEG-4 AVC/H.264 that can meet real time HDTV requirement and saves 64% of cycle count in average when compared with previous design is presented.
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