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Via (electronics)
Known as:
Deep vertical interconnect access
, Blind via
, DVIA (electronics)
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A via or VIA (Latin for path or way, also known as vertical interconnect access) is an electrical connection between layers in a physical electronic…
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Related topics
Related topics
33 relations
Annealed pyrolytic graphite
Antifuse
Bead probe technology
Copper interconnect
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Papers overview
Semantic Scholar uses AI to extract papers important to this topic.
Highly Cited
2009
Highly Cited
2009
Electromigration Failure Distributions of Cu/Low-$k$ Dual-Damascene Vias: Impact of the Critical Current Density and a New Reliability Extrapolation Methodology
A. Oates
,
M. H. Lin
IEEE transactions on device and materials…
2009
Corpus ID: 409304
We examine the effects of void morphology and critical current density (jc) on the electromigration failure distributions of Cu…
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Review
2008
Review
2008
Fabrication and characterization of robust through-silicon vias for silicon-carrier applications
P. Andry
,
C. Tsang
,
+4 authors
D. Manzer
IBM Journal of Research and Development
2008
Corpus ID: 40185913
As traditional CMOS scaling becomes progressively more difficult and less beneficial to overall system performance, three…
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Highly Cited
2008
Highly Cited
2008
High aspect ratio TSV copper filling with different seed layers
M. J. Wolf
,
Thomas Dretschkow
,
+6 authors
Herbert Reichl
Electronic Components and Technology Conference
2008
Corpus ID: 39265599
The paper addresses the through silicon via (TSV) filling using electrochemical deposition (ECD) of copper. The impact of seed…
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Highly Cited
2006
Highly Cited
2006
Factors affecting copper filling process within high aspect ratio deep vias for 3D chip stacking
Bioh Kim
,
C. Sharbono
,
T. Ritzdorf
,
Dan Schmauch Semitool
Electronic Components and Technology Conference
2006
Corpus ID: 21804485
Through-silicon-via (TSV) copper electrodes can provide shortest-length and highest-density connections with reduced signal delay…
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Highly Cited
2005
Highly Cited
2005
Low-resistance multi-walled carbon nanotube vias with parallel channel conduction of inner shells [IC interconnect applications]
M. Nihei
,
D. Kondo
,
+6 authors
Y. Awano
Proceedings of the IEEE International…
2005
Corpus ID: 9220519
We have succeeded in lowering the resistance of multi-walled carbon nanotube (MWNT) vias, using parallel channel conduction of…
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Highly Cited
1990
Highly Cited
1990
An electromagnetic approach for modeling high performance computer packages
B. Rubin
1990
Corpus ID: 58980229
Described here is an electromagnetic approach for the analysis of high-performance computer packages such as the thermal…
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Highly Cited
1983
Highly Cited
1983
Minimum-Via Topological Routing
C. Hsu
IEEE Trans. Comput. Aided Des. Integr. Circuits…
1983
Corpus ID: 17126741
A new approach to the two-dimensional routing utilizing two layers is proposed. It consists of two major steps, topological…
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Highly Cited
1983
Highly Cited
1983
Hierarchical channel router
Michael Burstein
,
R. Pelavin
Design Automation Conference
1983
Corpus ID: 15153458
The channel routing problem is a special care of the wire routing problem when interconnections have to be performed within a…
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Highly Cited
1983
Highly Cited
1983
Hierarchical Channel Router
M. Burstein
,
R. Pelavin
Design Automation Conference, Proceedings
1983
Corpus ID: 2244825
Highly Cited
1975
Highly Cited
1975
Capacitance models for integrated circuit metallization wires
A. Ruehli
,
P. Brennan
1975
Corpus ID: 62754797
New concepts are introduced relating aspects of circuit theory to the multicapacitances which can be obtained from a computer…
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