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Via (electronics)
Known as:
Deep vertical interconnect access
, Blind via
, DVIA (electronics)
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A via or VIA (Latin for path or way, also known as vertical interconnect access) is an electrical connection between layers in a physical electronic…
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Related topics
Related topics
33 relations
Annealed pyrolytic graphite
Antifuse
Bead probe technology
Copper interconnect
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Papers overview
Semantic Scholar uses AI to extract papers important to this topic.
2008
2008
300-Gb/s 24-channel bidirectional Si carrier transceiver Optochip for board-level interconnects
F. Doany
,
C. Schow
,
+6 authors
J. Kash
Electronic Components and Technology Conference
2008
Corpus ID: 25575719
A parallel optical transceiver module with 24-transmitter plus 24-receiver channels has been designed and fabricated. The…
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2007
2007
Carbon Nanotube/Copper Composites for Via Filling and Thermal Management
Y. Chai
,
Kai Zhang
,
M. Zhang
,
P. Chan
,
M. Yuen
Proceedings 57th Electronic Components and…
2007
Corpus ID: 26861314
With excellent current carrying capacity and extremely high thermal conductivity, carbon nanotube (CNT) has been proposed for…
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Highly Cited
2006
Highly Cited
2006
Factors affecting copper filling process within high aspect ratio deep vias for 3D chip stacking
Bioh Kim
,
C. Sharbono
,
T. Ritzdorf
,
Dan Schmauch Semitool
Electronic Components and Technology Conference
2006
Corpus ID: 21804485
Through-silicon-via (TSV) copper electrodes can provide shortest-length and highest-density connections with reduced signal delay…
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Highly Cited
2005
Highly Cited
2005
Low-resistance multi-walled carbon nanotube vias with parallel channel conduction of inner shells [IC interconnect applications]
M. Nihei
,
D. Kondo
,
+6 authors
Y. Awano
Proceedings of the IEEE International…
2005
Corpus ID: 9220519
We have succeeded in lowering the resistance of multi-walled carbon nanotube (MWNT) vias, using parallel channel conduction of…
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Highly Cited
2004
Highly Cited
2004
Targeted layout modifications for semiconductor yield/reliability enhancement
G. A. Allan
IEEE transactions on semiconductor manufacturing
2004
Corpus ID: 22441770
A new layout modification tool for the automation of layout modifications to improve the yield and reliability of semiconductor…
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Highly Cited
1997
Highly Cited
1997
New capabilities of OBIRCH method for fault localization and defect detection
K. Nikawa
,
S. Inoue
Asian Test Symposium
1997
Corpus ID: 20470034
We have improved the optical beam induced resistance change (OBIRCH) method so as to detect (1) a current path as small as 10-50…
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Highly Cited
1983
Highly Cited
1983
Minimum-Via Topological Routing
Chi-Ping Hsu
IEEE Trans. Comput. Aided Des. Integr. Circuits…
1983
Corpus ID: 17126741
A new approach to the two-dimensional routing utilizing two layers is proposed. It consists of two major steps, topological…
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Highly Cited
1983
Highly Cited
1983
Hierarchical Channel Router
M. Burstein
,
R. Pelavin
Design Automation Conference, Proceedings
1983
Corpus ID: 2244825
Highly Cited
1983
Highly Cited
1983
Hierarchical channel router
Michael Burstein
,
R. Pelavin
Design Automation Conference
1983
Corpus ID: 15153458
The channel routing problem is a special care of the wire routing problem when interconnections have to be performed within a…
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Highly Cited
1975
Highly Cited
1975
Capacitance models for integrated circuit metallization wires
A. Ruehli
,
P. Brennan
1975
Corpus ID: 62754797
New concepts are introduced relating aspects of circuit theory to the multicapacitances which can be obtained from a computer…
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