Factors affecting copper filling process within high aspect ratio deep vias for 3D chip stacking

  title={Factors affecting copper filling process within high aspect ratio deep vias for 3D chip stacking},
  author={Bruce Kim and Charles Sharbono and Tom Ritzdorf and David Schmauch},
  journal={56th Electronic Components and Technology Conference 2006},
  pages={6 pp.-}
Through-silicon-via (TSV) copper electrodes can provide shortest-length and highest-density connections with reduced signal delay and power consumption. The issues involved with making TSV processes manufacturable include: (a) via shape and angle control; (b) insulator, barrier, and seed deposition with good conformality and adhesion; (c) void-free via filling with copper; (d) metal removal by CMP; (e) wafer thinning with small total-thickness-variation and with no critical defects; (f) via… CONTINUE READING
Highly Cited
This paper has 60 citations. REVIEW CITATIONS
40 Citations
16 References
Similar Papers


Publications citing this paper.
Showing 1-10 of 40 extracted citations

61 Citations

Citations per Year
Semantic Scholar estimates that this publication has 61 citations based on the available data.

See our FAQ for additional information.


Publications referenced by this paper.
Showing 1-10 of 16 references

High Aspect Ratio Via Filling with Copper for 3D Integration

  • B. Kim
  • Proceedings of Semicon Korea 2006 STS,
  • 2006
1 Excerpt

3D Integration Technologies – An Overview

  • R. Chanchani
  • ECTC Annual Meeting, Professional Development…
  • 2005

A New Paradigm in Wafer Thinning”, PEAKS - Wafer Level Packaging

  • D. Scranton
  • 2005

Challenges in Copper Deep Via Plating”, PEAKS - Wafer Level Packaging

  • T. Dory
  • 2005

Future IC Go Vertical

  • P. Garrou
  • Semiconductor International,
  • 2005

Manufacturable Electrodeposition Processes for Advanced Packaging Applications

  • B. Kim
  • Annual Meeting of ISE
  • 2005

Sloped Sidewall DRIE Process Development for Through Silicon Vias (TSVs)

  • S. Polamreddy
  • IMAPS Device Packaging Conference,
  • 2005

Through-silicon Technology Applications Growing

  • J. Baliga
  • Semiconductor International,
  • 2005

Via-Filling by Copper Electroplating Using Current Waveform Control

  • K. Oyamada
  • Annual Meeting of ISE
  • 2005

Similar Papers

Loading similar papers…