Factors affecting copper filling process within high aspect ratio deep vias for 3D chip stacking

@article{Kim2006FactorsAC,
  title={Factors affecting copper filling process within high aspect ratio deep vias for 3D chip stacking},
  author={Bruce Kim and Charles Sharbono and Tom Ritzdorf and David Schmauch},
  journal={56th Electronic Components and Technology Conference 2006},
  year={2006},
  pages={6 pp.-}
}
Through-silicon-via (TSV) copper electrodes can provide shortest-length and highest-density connections with reduced signal delay and power consumption. The issues involved with making TSV processes manufacturable include: (a) via shape and angle control; (b) insulator, barrier, and seed deposition with good conformality and adhesion; (c) void-free via filling with copper; (d) metal removal by CMP; (e) wafer thinning with small total-thickness-variation and with no critical defects; (f) via… CONTINUE READING
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