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Through-silicon via
Known as:
TSV
, Through silicon via
, Through-silicon via (TSV)
In electronic engineering, a through-silicon via (TSV) is a vertical electrical connection (via) passing completely through a silicon wafer or die…
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Related topics
Related topics
16 relations
Back-illuminated sensor
Deep reactive-ion etching
Die (integrated circuit)
Electrical connection
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Broader (1)
Semiconductor device fabrication
Papers overview
Semantic Scholar uses AI to extract papers important to this topic.
Highly Cited
2016
Highly Cited
2016
InFO (Wafer Level Integrated Fan-Out) Technology
C. Tseng
,
Chung-Shi Liu
,
Chi-Hsi Wu
,
Douglas Yu
Electronic Components and Technology Conference
2016
Corpus ID: 31903044
A powerful integrated fan-out (InFO) wafer level system integration (WLSI) technology has been developed to integrate application…
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Highly Cited
2014
Highly Cited
2014
25.2 A 1.2V 8Gb 8-channel 128GB/s high-bandwidth memory (HBM) stacked DRAM with effective microbump I/O test methods using 29nm process and TSV
Dong-Uk Lee
,
Kyung Whan Kim
,
+14 authors
Sung-Joo Hong
IEEE International Solid-State Circuits…
2014
Corpus ID: 263889117
Increasing demand for higher-bandwidth DRAM drive TSV technology development. With the capacity of fine-pitch wide I/O [1], DRAM…
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Highly Cited
2011
Highly Cited
2011
Reliability challenges in 3D IC packaging technology
K. Tu
Microelectronics and reliability
2011
Corpus ID: 1865778
Highly Cited
2011
Highly Cited
2011
A 1.2V 12.8GB/s 2Gb mobile Wide-I/O DRAM with 4×128 I/Os using TSV-based stacking
Jung-Sik Kim
,
C. Oh
,
+20 authors
Young-Hyun Jun
IEEE International Solid-State Circuits…
2011
Corpus ID: 453667
Mobile DRAM is widely employed in portable electronic devices due to its feature of low power consumption. Recently, as the…
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Highly Cited
2011
Highly Cited
2011
A 1.2 V 12.8 GB/s 2 Gb Mobile Wide-I/O DRAM With 4 $\times$ 128 I/Os Using TSV Based Stacking
Jung-Sik Kim
,
C. Oh
,
+19 authors
Young-Hyun Jun
IEEE Journal of Solid-State Circuits
2011
Corpus ID: 27129807
A 1.2 V 1 Gb mobile SDRAM, having 4 channels with 512 DQ pins has been developed with 50 nm technology. It exhibits 330.6 mW read…
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Highly Cited
2010
Highly Cited
2010
Electrical Modeling and Characterization of Through Silicon via for Three-Dimensional ICs
G. Katti
,
M. Stucchi
,
K. D. Meyer
,
W. Dehaene
IEEE Transactions on Electron Devices
2010
Corpus ID: 28295279
Three-dimensional ICs provide a promising option to build high-performance compact SoCs by stacking one or more chips vertically…
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Highly Cited
2009
Highly Cited
2009
Thermal management of 3D IC integration with TSV (through silicon via)
J. Lau
,
T. Yue
Electronic Components and Technology Conference
2009
Corpus ID: 32620989
Thermal performances of 3D stacked TSV (through silicon via) chips filled with copper are investigated based on heat-transfer CFD…
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Highly Cited
2009
Highly Cited
2009
High-Density Through Silicon Vias for 3-D LSIs
M. Koyanagi
,
T. Fukushima
,
Tetsu Tanaka
Proceedings of the IEEE
2009
Corpus ID: 32817916
High density through silicon via (TSV) is a key in fabricating three-dimensional (3-D) large-scale integration (LSI). We have…
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2009
2009
Through silicon via (TSV) equalizer
Joohee Kim
,
Eakhwan Song
,
+5 authors
Joungho Kim
IEEE 18th Conference on Electrical Performance of…
2009
Corpus ID: 25397819
Through silicon via (TSV) is a promising vertical interconnection method to achieve a 3-dimensional integrated circuit (3D IC…
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Review
2008
Review
2008
Three-dimensional silicon integration
J. Knickerbocker
,
P. Andry
,
+13 authors
S. Wright
IBM Journal of Research and Development
2008
Corpus ID: 7163354
Three-dimensional (3D) silicon integration of active devices with through-silicon vias (TSVs), thinned silicon, and silicon-to…
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