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OpenRISC 1200
Known as:
OR1200
A synthesizable CPU core, it was for many years maintained by developers at OpenCores.org, although, since 2015, that activity has now been taken…
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Related topics
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18 relations
ARM architecture
Application-specific integrated circuit
CPU cache
Dhrystone
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Papers overview
Semantic Scholar uses AI to extract papers important to this topic.
2019
2019
Radiation Hardened Design of Pipeline and Register File in Processor
Liyi Xiao
,
Yuan-Gang Wang
,
Zu-Qiang Zhang
,
Jiaqiang Li
,
Jie Li
International Conference on ASIC
2019
Corpus ID: 211060346
With the development of aerospace technology and integrated circuit (IC) technology, the processor, as the core component of the…
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2017
2017
Exploiting the analog properties of digital circuits for malicious hardware
Kaiyuan Yang
,
Matthew Hicks
,
Qing Dong
,
T. Austin
,
D. Sylvester
Communications of the ACM
2017
Corpus ID: 29707811
While the move to smaller transistors has been a boon for performance it has dramatically increased the cost to fabricate chips…
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2015
2015
Event-driven transient error propagation: A scalable and accurate soft error rate estimation approach
Mojtaba Ebrahimi
,
Razi Seyyedi
,
Liang Chen
,
M. Tahoori
Asia and South Pacific Design Automation…
2015
Corpus ID: 16621706
Fast and accurate soft error vulnerability assessment is an integral part of cost-effective robust system design. The de facto…
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2014
2014
EAGLE: A regression model for fault coverage estimation using a simulation based metric
S. Mirkhani
,
J. Abraham
International Test Conference
2014
Corpus ID: 6660928
Evaluating the fault coverage of manufacturing tests has become a time-consuming process due to today's large and complex digital…
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2013
2013
Algorithm and Architecture Design of Human–Machine Interaction in Foreground Object Detection With Dynamic Scene
T. Tsai
,
Chung-Yuan Lin
,
Sz-Yan Li
IEEE transactions on circuits and systems for…
2013
Corpus ID: 23402361
In the field of intelligent visual surveillance, the topic of tolerating background motions while detecting foreground motions in…
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2011
2011
Variation-Conscious Formal Timing Verification in RTL
Jayanand Asok Kumar
,
Shobha Vasudevan
24th Internatioal Conference on VLSI Design
2011
Corpus ID: 37066413
ariations in timing can occur due to multiple sources on a chip. Many circuit level statistical techniques are used to analyze…
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2010
2010
UART integration in OR1200 based SOC design
Zhichao Zhang
,
Wu-chen Wu
International Conference on Computer Engineering…
2010
Corpus ID: 14552313
UART is a kind of serial communication interface. It is widely used in data exchange between microprocessor and peripheral…
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2009
2009
Compiler/hardware assisted application code and data security in embedded systems
Chunguang Bu
,
Xiang Wang
,
Chi Zhang
,
Jizhong Liu
,
Xiaodong Wang
,
Baosen Li
Symposium on Dependable Autonomic and Secure…
2009
Corpus ID: 16014620
Embedded systems have stepped deeper into Integrated Avionics systems, and security is becoming an important concern. Most…
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2008
2008
Performance Improvement and Low Power Design of Embedded Processor
Hongkyun Jung
,
Hyoungjun Kim
,
Kwangmyoung Kang
,
K. Ryoo
Third International Conference on Convergence and…
2008
Corpus ID: 14655956
This paper presents a branch prediction algorithm and a 4-way set-associative cache for performance improvement of 32-bit RISC…
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2007
2007
Secure IP downloading for SRAM FPGAs
J. Castillo
,
P. Huerta
,
J. Martínez
Microprocessors and microsystems
2007
Corpus ID: 1553625
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