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OpenRISC 1200
Known as:
OR1200
A synthesizable CPU core, it was for many years maintained by developers at OpenCores.org, although, since 2015, that activity has now been taken…
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Related topics
Related topics
18 relations
ARM architecture
Application-specific integrated circuit
CPU cache
Dhrystone
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Papers overview
Semantic Scholar uses AI to extract papers important to this topic.
2018
2018
Defeating Hardware Trojans trough on-chip Software Obfuscation
Luca Sasselli
2018
Corpus ID: 69841016
Due to the competitive nature of the embedded-system market, and the ever-increasing complexity of integrated circuits, most…
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2017
2017
Design of High-speed Dynamic Packet Filtering Firewall for IPv6 based on FPGA
Bing Li
,
Pengcheng Cai
,
Xin Guo
,
Long-Fei Zhang
2017
Corpus ID: 54791165
Network security issues are becoming increasingly acute. A computer network exposed to the Internet without any security…
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2013
2013
High Speed Fault Injection Tool Implemented With Verilog HDL on FPGA for Testing Fault Tolerance Designs
G. G. Reddy
,
A. Yadav
,
Y. Mahesh
2013
Corpus ID: 11559046
This paper presents an FPGA-based fault injection tool, called FITO that supports several synthesizable fault models for…
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2013
2013
Design of AMBA AHB interface around OpenRISC 1200 processor and comparing the implementation with existing architecture
Bhaumik Vaidya
,
Jaydeep Bhatt
,
Ashwin Patel
,
Anupam Devani
2013
Corpus ID: 56413895
Open source Components are gaining popularity because they not only reduce the cost significantly but also provide power to the…
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2012
2012
PERFORMANCE EVALUATION OF OR1200 PROCESSOR WITH EVOLUTIONARY PARALLEL HPRC USING GEP
R. Maheswari
,
V. Pattabiraman
Soft Computing Models in Industrial and…
2012
Corpus ID: 16277749
In this fast computing era, most of the embedded system requires more computing power to complete the complex function/ task at…
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2009
2009
Design of Embedded Ethernet Based on OR1200 microprocessor
De-Xue Zhang
2009
Corpus ID: 63961331
While many people domestic and overseas are focusing on combing embedded systems with Internet, Combining the development of…
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2009
2009
SHARPE: Variation-Aware Formal Statistical Timing Analysis in RTL
Jayanand Asok Kumar
,
Shobha Vasudevan
2009
Corpus ID: 56234191
Variations in timing can occur due to multiple sources on a chip. Many circuit level statistical techniques are used to analyze…
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2009
2009
Embedded system design of open source microprocessor OR1200
Han Jiao
2009
Corpus ID: 114119082
This paper introduces the design schedule of embedded SoC based on OpenRISC1200 which is a 32 bit open source code.The hardware…
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2008
2008
Real-time trace for performance analysis in OR1200 = 성능 분석을 위한 리얼타임 트레이스
Byung-Chul Hong
,
병철 홍
2008
Corpus ID: 67700070
2005
2005
MP3 decoding on OpenRISC 1200, an open source RISC microcontroller.
Olav Gulling
2005
Corpus ID: 106820998
OpenRISC er en fritt tilgjengelig mikrokontroller, med tilhorende utviklingsverktoy. Ekstra moduler kan kobles til den, og dermed…
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