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Near-Threshold Computing: Reclaiming Moore's Law Through Energy Efficient Integrated Circuits
- R. Dreslinski, M. Wieckowski, D. Blaauw, D. Sylvester, T. Mudge
- Computer ScienceProceedings of the IEEE
- 22 January 2010
The barriers to the widespread adoption of near-threshold computing are explored and current work aimed at overcoming these obstacles are described.
A Portable 2-Transistor Picowatt Temperature-Compensated Voltage Reference Operating at 0.5 V
- Mingoo Seok, G. Kim, D. Blaauw, D. Sylvester
- EngineeringIEEE Journal of Solid-State Circuits
- 31 August 2012
The proposed voltage reference for use in ultra-low power systems, referred to as the 2T voltage reference, which has been demonstrated in silicon across three CMOS technologies, is proposed, showing the design exhibits comparable spreads in TC and output voltage to existing voltage references in the literature.
New paradigm of predictive MOSFET and interconnect modeling for early circuit simulation
- Yu Cao, Takashi Sato, M. Orshansky, D. Sylvester, C. Hu
- Computer Science, EngineeringProceedings of the IEEE Custom Integrated…
A new paradigm of predictive MOSFET and interconnect modeling is introduced to specifically address SPICE compatible parameters for future technology generations and comparisons with published data and 2D simulations are used to verify this predictive technology model.
Neural Cache: Bit-Serial In-Cache Acceleration of Deep Neural Networks
- Charles Eckert, Xiaowei Wang, R. Das
- Computer ScienceACM/IEEE 45th Annual International Symposium on…
- 9 May 2018
This paper presents the Neural Cache architecture, which re-purposes cache structures to transform them into massively parallel compute units capable of running inferences for Deep Neural Networks, and shows that the proposed architecture can improve inference latency and reduce power consumption.
Statistical Analysis and Optimization for VLSI: Timing and Power
- Ashish Srivastava, D. Sylvester, D. Blaauw
- Computer Science, EconomicsSeries on Integrated Circuits and Systems
- 21 June 2005
The next generation of statistical models and techniques will be used to improve the quality of existing models and provide new insights into the determinants of yield and power.
Bubble Razor: Eliminating Timing Margins in an ARM Cortex-M3 Processor in 45 nm CMOS Using Architecturally Independent Error Detection and Correction
B Bubble Razor, an architecturally independent approach to timing error detection and correction that avoids hold-time issues and enables large timing speculation windows is proposed and implemented on an ARM Cortex-M3 microprocessor in 45 nm CMOS to demonstrate the technique's automated capability.
Vicis: A reliable network for unreliable silicon
- D. Fick, A. DeOrio, Jin Hu, V. Bertacco, D. Blaauw, D. Sylvester
- Computer Science46th ACM/IEEE Design Automation Conference
- 26 July 2009
This work presents Vicis, an ElastIC-style NoC that can tolerate the loss of many network components due to wearout induced hard faults, and shows that with stuck-at fault rates as high as 1 in 2000 gates, Vicis will continue to operate with approximately half of its routers still functional and communicating.
Theoretical and practical limits of dynamic voltage scaling
- Bo Zhai, D. Blaauw, D. Sylvester, K. Flautner
- PhysicsProceedings. 41st Design Automation Conference, .
- 7 June 2004
It is shown that extending the voltage range below 1/2 Vdd will improve the energy efficiency for most processor designs, while extending this range to subthreshold operation is beneficial only for very specific applications and that operation deep in the subth threshold voltage range is never energy-efficient.
Parametric yield estimation considering leakage variability
- Rajeev R. Rao, A. Devgan, D. Blaauw, D. Sylvester
- EngineeringProceedings. 41st Design Automation Conference, .
- 7 June 2004
A new chip-level statistical method to estimate the total leakage current in the presence of within-die and die-to-die variability is presented, and an integrated approach to accurately estimate the yield loss when both frequency and power limits are imposed on a design is presented.
A2: Analog Malicious Hardware
- Kaiyuan Yang, Matthew Hicks, Qing Dong, T. Austin, D. Sylvester
- Computer ScienceIEEE Symposium on Security and Privacy (SP)
- 22 May 2016
This paper shows how a fabrication-time attacker can leverage analog circuits to create a hardware attack that is small (i.e., requires as little as one gate) and stealthy and requires an unlikely trigger sequence before effecting a chip's functionality.