T. Austin

Publications185
h-index56
Citations21,436
Highly Influential Citations2,060
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MiBench: A free, commercially representative embedded benchmark suite
TLDR
A new version of SimpleScalar that has been adapted to the ARM instruction set is used to characterize the performance of the benchmarks using configurations similar to current and next generation embedded processors.
The SimpleScalar tool set, version 2.0
This document describes release 2.0 of the SimpleScalar tool set, a suite of free, publicly available simulation tools that offer both detailed and high-performance simulation of modern…
SimpleScalar: An Infrastructure for Computer System Modeling
TLDR
The SimpleScalar tool set provides an infrastructure for simulation and architectural modeling that can model a variety of platforms ranging from simple unpipelined processors to detailed dynamically scheduled microarchitectures with multiple-level memory hierarchies.
Razor: a low-power pipeline based on circuit-level timing speculation
  • D. Ernst, N. Kim, T. Mudge
  • Computer Science
    Proceedings. 36th Annual IEEE/ACM International…
  • 3 December 2003
TLDR
A new approach to DVS is proposed, called Razor, based on dynamic detection and correction of circuit timing errors, to tune the supply voltage by monitoring the error rate during circuit operation, thereby eliminating the need for voltage margins and exploiting the data dependence of circuit delay.
A systematic methodology to compute the architectural vulnerability factors for a high-performance microprocessor
TLDR
A method for generating per-structure AVF estimates for microprocessor error rates is described, identifying numerous cases, such as prefetches, dynamically dead code, and wrong-path instructions, in which a fault do not affect, correct execution.
Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation
TLDR
A solution by which the circuit can be operated even below the ‘critical’ voltage, so that no margins are required and thus more energy can be saved.
DIVA: a reliable substrate for deep submicron microarchitecture design
  • T. Austin
  • Computer Science, Engineering
    MICRO-32. Proceedings of the 32nd Annual ACM/IEEE…
  • 16 November 1999
TLDR
It is argued that the DIVA checker should lend itself to functional and electrical verification better than a complex core processor, and overall design cost can be dramatically reduced because designers need only verify the correctness of the checker unit.
Evaluating Future Microprocessors: the SimpleScalar Tool Set
TLDR
An anview of the SimpleScalar tool set is given, show how to obtain, install and use it, and details about the tools’ internals are discussed.
A Systematic Methodology to Compute the Architectural Vulnerability Factors for a High-Performance Microprocessor
TLDR
This paper identifies numerous cases, such as prefetches, dynamicallydead code, and wrong-path instructions, in which a fault will not affect correct execution, and shows AVFs of 28% and 9% for the instruction queue and execution units, respectively,averaged across dynamic sections of the entire CPU2000benchmark suite.
Leakage Current: Moore's Law Meets Static Power
Off-state leakage is static power, current that leaks through transistors even when they are turned off. The other source of power dissipation in today's microprocessors, dynamic power, arises from…
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