Hongkyun Jung

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This paper describes the development of a synthesizable SoC platform using OpenCores processor and WISHBONE on-chip bus. The platform includes a OpenRISC 1200 microprocessor, some basic peripherals, such as on-chip RAM, GPIO, UART, debug interface, VGA controller and WISHBONE bus and uses the set of development environment including compiler, assembler,(More)
This paper presents a branch prediction algorithm and a 4-way set-associative cache for performance improvement of an embedded RISC core and a clock-gating algorithm with observability don’t care (ODC) operation to reduce the power consumption of the core. The branch prediction algorithm has a structure using a branch target buffer (BTB) and 4-way set(More)
This paper presents a branch prediction algorithm and a 4-way set-associative cache for performance improvement of 32-bit RISC processor and a clock gating algorithm using ODC (observability don't care) operation for a low-power processor. The branch prediction algorithm has a structure using BTB (branch target buffer) and 4-way set associative cache using(More)
We propose a multimedia SoC platform with a crossbar on-chip bus which can reduce the bottleneck of on-chip communication by multi-channels. The platform consists of RISC processor, WISHBONE crossbar on-chip bus, memory interface, VGA controller, DMA, AC97 controller, debug interface and UART. The crossbar on-chip bus supports up to 8 masters and 16 slaves,(More)
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