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Architectural state
The architectural state is the part of the CPU which holds the state of a process, this includes: * Control registers * Instruction Flag Registers…
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Related topics
Related topics
8 relations
Arithmetic logic unit
Barrel processor
Central processing unit
Control register
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Papers overview
Semantic Scholar uses AI to extract papers important to this topic.
2020
2020
FENL: an ISE to mitigate analogue micro-architectural leakage
Si Gao
,
Ben Marshall
,
D. Page
,
T. Pham
IACR Trans. Cryptogr. Hardw. Embed. Syst.
2020
Corpus ID: 212670312
Ge et al. [GYH18] propose the augmented ISA (or aISA), a central tenet of which is the selective exposure of micro-architectural…
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2014
2014
BarrierPoint: Sampled simulation of multi-threaded applications
Trevor E. Carlson
,
W. Heirman
,
K. Craeynest
,
L. Eeckhout
IEEE International Symposium on Performance…
2014
Corpus ID: 9491064
Sampling is a well-known technique to speed up architectural simulation of long-running workloads while maintaining accurate…
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2014
2014
Fast Dynamic Binary Rewriting for flexible thread migration on shared-ISA heterogeneous MPSoCs
G. Georgakoudis
,
Dimitrios S. Nikolopoulos
,
H. Vandierendonck
,
S. Lalis
International Conference on Embedded Computer…
2014
Corpus ID: 4982789
Heterogeneous MPSoCs where different types of cores share a baseline ISA but implement different operational accelerators combine…
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Highly Cited
2011
Highly Cited
2011
A 45 nm Resilient Microprocessor Core for Dynamic Variation Tolerance
K. Bowman
,
J. Tschanz
,
+8 authors
V. De
IEEE Journal of Solid-State Circuits
2011
Corpus ID: 1196010
A 45 nm microprocessor core integrates resilient error-detection and recovery circuits to mitigate the clock frequency (FCLK…
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Review
2011
Review
2011
Error Tolerance in Server Class Processors
J. Rivers
,
M. Gupta
,
Jeonghee Shin
,
P. Kudva
,
P. Bose
IEEE Transactions on Computer-Aided Design of…
2011
Corpus ID: 14926691
This paper provides: 1) a very brief motivation and technological trend data to show why hard and soft errors are expected to be…
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2011
2011
Portable trace compression through instruction interpretation
Svilen Kanev
,
R. Cohn
(IEEE ISPASS) IEEE INTERNATIONAL SYMPOSIUM ON…
2011
Corpus ID: 73803
Execution traces are a useful tool in studying processor and program behavior. However, the amount of information that needs to…
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2009
2009
Constraint-Based Local Search for the Automatic Generation of Architectural Tests
Pascal Van Hentenryck
,
Carleton Coffrin
,
B. Gutkovich
CP
2009
Corpus ID: 6940968
This paper considers the automatic generation of architectural tests (ATGP), a fundamental problem in processor validation. ATGPs…
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Highly Cited
2007
Highly Cited
2007
Perturbation-based Fault Screening
Paul Racunas
,
Kypros Constantinides
,
S. Manne
,
S. Mukherjee
IEEE 13th International Symposium on High…
2007
Corpus ID: 9771850
Fault screeners are a new breed of fault identification technique that can probabilistically detect if a transient fault has…
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2006
2006
CP with Architectural State Lookup for Functional Test Generation
B. Gutkovich
,
A. Moss
IEEE International High Level Design Validation…
2006
Corpus ID: 2835992
Constraint programming (CP) is a powerful technology that has proved very useful in random functional test generation. On the…
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Highly Cited
2004
Highly Cited
2004
Characterizing the effects of transient faults on a high-performance processor pipeline
Nicholas J. Wang
,
Justin Quek
,
Todd M. Rafacz
,
Sanjay J. Patel
International Conference on Dependable Systems…
2004
Corpus ID: 6204449
The progression of implementation technologies into the sub-100 nanometer lithographies renew the importance of understanding and…
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