• Publications
  • Influence
Flash correct-and-refresh: Retention-aware error management for increased flash memory lifetime
  • Y. Cai, G. Yalcin, +4 authors K. Mai
  • Computer Science
  • IEEE 30th International Conference on Computer…
  • 30 September 2012
TLDR
We present flash correct-and-refresh (FCR) techniques, which offer a low-overhead mechanism to significantly improve the lifetime of flash-based data storage systems, requiring only modifications to the SSD controller firmware or driver software. Expand
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Redundant Memory Mappings for fast access to large memories
TLDR
This paper proposes Redundant Memory Mappings (RMM), which leverage ranges of pages and provides an efficient, alternative representation of many virtual-to-physical mappings. Expand
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DiDi: Mitigating the Performance Impact of TLB Shootdowns Using a Shared TLB Directory
TLDR
We characterize the impact of TLB shoot downs on multiprocessor performance and scalability, and present the design of a scalable TLB coherency mechanism that eliminates the need for costly Inter-Proceessor Interrupts. Expand
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EazyHTM: EAger-LaZY hardware Transactional Memory
TLDR
We show a scalable HTM architecture that performs comparably to the state-of-the-art and can be implemented by minor modifications to the MESI protocol rather than re-engineering it from the ground up. Expand
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Out-of-order commit processors
TLDR
We propose to increase the capacity of future processors by augmenting the number of in-flight instructions in order to tolerate a higher memory latency. Expand
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Atomic quake: using transactional memory in an interactive multiplayer game server
TLDR
Transactional Memory (TM) is being studied widely as a new technique for synchronizing concurrent accesses to shared memory data structures for use in multi-core systems. Expand
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Toward kilo-instruction processors
TLDR
In this paper we show that, in order to overcome this resource-scalability problem, the way in which critical processor resources are managed must be changed. Expand
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Advanced Pattern based Memory Controller for FPGA based HPC applications
TLDR
The ever-increasing complexity of high-performance computing applications limits performance due to memory constraints in FPGAs. Expand
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The limits of software transactional memory (STM): dissecting Haskell STM applications on a many-core environment
TLDR
We present a Haskell Transactional Memory benchmark to provide a comprehensive application suite for the use of Software Transactual Memory (STM) researchers. Expand
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RMS-TM: a comprehensive benchmark suite for transactional memory systems
TLDR
In this paper, we introduce RMS-TM, a Transactional Memory benchmark suite composed of seven real-world applications from the Recognition, Mining and Synthesis (RMS) domain. Expand
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