• Publications
  • Influence
Flash correct-and-refresh: Retention-aware error management for increased flash memory lifetime
  • Y. Cai, G. Yalcin, +4 authors K. Mai
  • Computer Science
  • IEEE 30th International Conference on Computer…
  • 30 September 2012
tl;dr
We present flash correct-and-refresh (FCR) techniques, which offer a low-overhead mechanism to significantly improve the lifetime of flash-based data storage systems, requiring only modifications to the SSD controller firmware or driver software. Expand
  • 175
  • 23
  • Open Access
Redundant Memory Mappings for fast access to large memories
tl;dr
This paper proposes Redundant Memory Mappings (RMM), which leverage ranges of pages and provides an efficient, alternative representation of many virtual-to-physical mappings. Expand
  • 93
  • 20
  • Open Access
DiDi: Mitigating the Performance Impact of TLB Shootdowns Using a Shared TLB Directory
tl;dr
We characterize the impact of TLB shoot downs on multiprocessor performance and scalability, and present the design of a scalable TLB coherency mechanism that eliminates the need for costly Inter-Proceessor Interrupts. Expand
  • 84
  • 13
  • Open Access
EazyHTM: EAger-LaZY hardware Transactional Memory
tl;dr
We show a scalable HTM architecture that performs comparably to the state-of-the-art and can be implemented by minor modifications to the MESI protocol rather than re-engineering it from the ground up. Expand
  • 109
  • 9
  • Open Access
Out-of-order commit processors
tl;dr
We propose to increase the capacity of future processors by augmenting the number of in-flight instructions in order to tolerate a higher memory latency. Expand
  • 144
  • 6
  • Open Access
Atomic quake: using transactional memory in an interactive multiplayer game server
tl;dr
Transactional Memory (TM) is being studied widely as a new technique for synchronizing concurrent accesses to shared memory data structures for use in multi-core systems. Expand
  • 88
  • 5
  • Open Access
Toward kilo-instruction processors
tl;dr
In this paper we show that, in order to overcome this resource-scalability problem, the way in which critical processor resources are managed must be changed. Expand
  • 84
  • 5
  • Open Access
Advanced Pattern based Memory Controller for FPGA based HPC applications
tl;dr
The ever-increasing complexity of high-performance computing applications limits performance due to memory constraints in FPGAs. Expand
  • 32
  • 4
  • Open Access
The limits of software transactional memory (STM): dissecting Haskell STM applications on a many-core environment
tl;dr
We present a Haskell Transactional Memory benchmark to provide a comprehensive application suite for the use of Software Transactual Memory (STM) researchers. Expand
  • 62
  • 4
  • Open Access
RMS-TM: a comprehensive benchmark suite for transactional memory systems
tl;dr
In this paper, we introduce RMS-TM, a Transactional Memory benchmark suite composed of seven real-world applications from the Recognition, Mining and Synthesis (RMS) domain. Expand
  • 30
  • 4
  • Open Access