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McPAT: An integrated power, area, and timing modeling framework for multicore and manycore architectures
TLDR
Combining power, area, and timing results of McPAT with performance simulation of PARSEC benchmarks at the 22nm technology node for both common in-order and out-of-order manycore designs shows that when die cost is not taken into account clustering 8 cores together gives the best energy-delay product, whereas when cost is taking into account configuring clusters with 4 cores gives thebest EDA2P and EDAP. Expand
Simultaneous multithreading: Maximizing on-chip parallelism
TLDR
Simultaneous multithreading has the potential to achieve 4 times the throughput of a superscalar, and double that of fine-grain multi-threading, and is an attractive alternative to single-chip multiprocessors. Expand
Single-ISA heterogeneous multi-core architectures for multithreaded workload performance
TLDR
This paper examines two single-ISA heterogeneous multi-core architectures in detail, demonstrating dynamic core assignment policies that provide significant performance gains over naive assignment, and even outperform the best static assignment. Expand
Exploiting Choice: Instruction Fetch and Issue on an Implementable Simultaneous Multithreading Processor
TLDR
This paper presents an architecture for simultaneous multithreading that minimizes the architectural impact on the conventional superscalar design, has minimal performance impact on a single thread executing alone, and achieves significant throughput gains when running multiple threads. Expand
Single-ISA heterogeneous multi-core architectures: the potential for processor power reduction
TLDR
This paper proposes and evaluates single-ISA heterogeneous multi-core architectures as a mechanism to reduce processor power dissipation and results indicate a 39% average energy reduction while only sacrificing 3% in performance. Expand
Single-ISA Heterogeneous Multi-Core Architectures: The Potential for Processor Power Reduction
TLDR
This paper proposes and evaluates single-ISA heterogeneousmulti-core architectures as a mechanism to reduceprocessor power dissipation and results indicate a 39% average energy reduction while only sacrificing 3% in performance. Expand
Handling long-latency loads in a simultaneous multithreading processor
TLDR
It is shown that in many cases it is better to free the resources associated with a stalled thread rather than keep that thread ready to immediately begin execution upon return of the loaded data. Expand
The McPAT Framework for Multicore and Manycore Architectures: Simultaneously Modeling Power, Area, and Timing
TLDR
Combining power, area, and timing results of McPAT with performance simulation of PARSEC benchmarks for manycore designs at the 22nm technology shows that 8-core clustering gives the best energy-delay product, whereas when die area is taken into account, 4-core clusters give the best EDA2P and EDAP. Expand
Symbiotic jobscheduling for a simultaneous mutlithreading processor
TLDR
It is demonstrated that performance on a hardware multithreaded processor is sensitive to the set of jobs that are coscheduled by the operating system jobscheduler, and that a small sample of the possible schedules is sufficient to identify a good schedule quickly. Expand
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