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Optimizing FPGA-based Accelerator Design for Deep Convolutional Neural Networks
Convolutional neural network (CNN) has been widely employed for image recognition because it can achieve high accuracy by emulating behavior of optic nerves in living creatures. Recently, rapidExpand
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High-Level Synthesis for FPGAs: From Prototyping to Deployment
Escalating system-on-chip design complexity is pushing the design community to raise the level of abstraction beyond register transfer level. Despite the unsuccessful adoptions of early generationsExpand
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FlowMap: an optimal technology mapping algorithm for delay optimization in lookup-table based FPGA designs
  • J. Cong, Y. Ding
  • Computer Science
  • IEEE Trans. on CAD of Integrated Circuits and…
  • 8 November 1992
The field programmable gate-array (FPGA) has become an important technology in VLSI ASIC designs. In the past few years, a number of heuristic algorithms have been proposed for technology mapping inExpand
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A thermal-driven floorplanning algorithm for 3D ICs
As the technology progresses, interconnect delays have become bottlenecks of chip performance. 3D integrated circuits are proposed as one way to address this problem. However, thermal problem is aExpand
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Caffeine: Towards uniformed representation and acceleration for deep convolutional neural networks
With the recent advancement of multilayer convolutional neural networks (CNN), deep learning has achieved amazing success in many areas, especially in visual content understanding and classification.Expand
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CMP network-on-chip overlaid with multi-band RF-interconnect
In this paper, we explore the use of multi-band radio frequency interconnect (or RF-I) with signal propagation at the speed of light to provide shortcuts in a many core network-on-chip (NoC) meshExpand
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Bounded-skew clock and Steiner routing
We study the minimum-cost bounded-skew routing tree problem under the pathlength (linear) and Elmore delay models. This problem captures several engineering tradeoffs in the design of routingExpand
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A scalable micro wireless interconnect structure for CMPs
This paper describes an unconventional way to apply wireless networking in emerging technologies. It makes the case for using a two-tier hybrid wireless/wired architecture to interconnect hundreds toExpand
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mPL6: enhanced multilevel mixed-size placement
The multilevel placement package mPL6 combines improved implementations of the global placer mPL5 (ISPD05) and the XDP legalizer and detailed placer (ASPDAC06). It consistently produces robust,Expand
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Thermal via planning for 3-D ICs
  • J. Cong, Yan Zhang
  • Computer Science
  • ICCAD-. IEEE/ACM International Conference on…
  • 31 May 2005
Heat dissipation is one of the most serious challenges in 3-D IC designs. One effective way of reducing circuit temperature is to introduce thermal through-the-silicon (TTS) vias. In this paper, weExpand
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