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Three-dimensional integrated circuit
Known as:
3D Computer Chip
, Bond
, 3DS (die stacking)
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In microelectronics, a three-dimensional integrated circuit (3D IC) is an integrated circuit manufactured by stacking silicon wafers and/or dies and…
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Related topics
Related topics
38 relations
Bandwidth (signal processing)
Bus (computing)
CMOS
Central processing unit
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Broader (1)
Semiconductor device fabrication
Papers overview
Semantic Scholar uses AI to extract papers important to this topic.
2011
2011
Full-chip through-silicon-via interfacial crack analysis and optimization for 3D IC
Moongon Jung
,
Xi Liu
,
S. Sitaraman
,
D. Pan
,
S. Lim
IEEE/ACM International Conference on Computer…
2011
Corpus ID: 665577
In this work, we propose an efficient and accurate full-chip through-silicon-via (TSV) interfacial crack analysis flow and design…
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Highly Cited
2011
Highly Cited
2011
How to select adhesive materials for temporary bonding and de-bonding of 200mm and 300mm thin-wafer handling for 3D IC integration?
W. Tsai
,
H. Chang
,
+7 authors
M. Kao
Electronic Components and Technology Conference
2011
Corpus ID: 34971449
Handling and shipping thin wafers (≦200μm) through all the semiconductor fabrication and packaging assembly processes are very…
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Highly Cited
2010
Highly Cited
2010
Fine pitch chip interconnection technology for 3D integration
Jihwan. Hwang
,
Jongyeon Kim
,
W. Kwon
,
U. Kang
,
T. Cho
,
Sayoon Kang
Electronic Components and Technology Conference
2010
Corpus ID: 20454949
3D-IC packaging using through silicon via technology has been extensively developed to meet small form factor and low power…
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Highly Cited
2009
Highly Cited
2009
Study of 15µm pitch solder microbumps for 3D IC integration
A. Yu
,
J. Lau
,
+7 authors
D. Kwong
Electronic Components and Technology Conference
2009
Corpus ID: 20204158
Developments of ultra fine pitch and high density solder microbumps and assembly process for low cost 3D stacking technologies…
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2009
2009
Ultrafine-pitch C2 flip chip interconnections with solder-capped Cu pillar bumps
Y. Orii
,
K. Toriyama
,
+6 authors
C. Feger
Electronic Components and Technology Conference
2009
Corpus ID: 13205813
PoP structures have been used widely in digital consumer electronics products such as digital still cameras and mobile phones…
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2007
2007
Scaling Three-Dimensional SOI Integrated-Circuit Technology
C.K. Chen
,
K. Warner
,
+5 authors
C. Keast
IEEE International SOI Conference
2007
Corpus ID: 22282635
In this paper, we describe details of our bonding protocol for 150-mm diameter wafers, leading to a 50% increase in oxide-oxide…
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Highly Cited
2007
Highly Cited
2007
Two 10Gb/s/pin Low-Power Interconnect Methods for 3D ICs
Q. Gu
,
Zhiwei Xu
,
J. Ko
,
Mau-Chung Frank Chang
IEEE International Solid-State Circuits…
2007
Corpus ID: 206995369
Two RF techniques are combined with capacitive coupling interconnect to form ultra-wide-bandwidth impulse interconnect and RF…
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2006
2006
Performance Trend in Three-Dimensional Integrated Circuits
Hao Hua
,
C. Mineo
,
K. Schoienfliess
,
A. Sule
,
S. Melamed
,
W. R. Davis
International Interconnect Technology Conference
2006
Corpus ID: 17377371
3DICs are motivated by the expectation of better performance over their 2D counterparts; however, non-idealities threaten to…
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2004
2004
Design automation and analysis of three-dimensional integrated circuits
Shamik Das
2004
Corpus ID: 2867133
This dissertation concerns the design of circuits and systems for an emerging technology known as three-dimensional integration…
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1995
1995
Gigabit-rate optical-signal transmission using vertical-cavity surface-emitting lasers with large-core plastic-cladding fibers
H. Kosaka
,
K. Dutta
,
K. Kurihara
,
Y. Sugimoto
,
K. Kasahara
IEEE Photonics Technology Letters
1995
Corpus ID: 9566718
We have demonstrated multi-gigabit-rate large-signal modulation of vertical-cavity bottom-surface-emitting lasers (VCSELs…
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