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Three-dimensional integrated circuit (3D IC) with through-silicon-via (TSV) is believed to offer new levels of efficiency, power, performance, and form-factor advantages over the conventional 2D IC. However, 3D IC involves disruptive manufacturing technologies compared to conventional 2D IC. TSVs cause significant thermomechanical stress that may seriously(More)
Several recent works have demonstrated the benefits of through-silicon-via (TSV) based 3D integration [1-4], but none of them involves a fully functioning multicore processor and memory stacking. 3D-MAPS (3D Massively Parallel Processor with Stacked Memory) is a two-tier 3D IC, where the logic die consists of 64 general-purpose processor cores running at(More)
—With the extensive research on through-silicon-via (TSV) and die-stacking technology from both academia and industry, mainstream production of 3D ICs is expected in a near future. However, power delivery is believed to be one of the most challenging problems in 3D ICs. A main objective of the 3D power/ground (P/G) network optimization is to minimize the(More)
—The 3D IC integration using through-silicon-vias (TSV) has gained tremendous momentum recently for industry adoption. However, as TSV involves disruptive manufacturing technologies, new modeling and design techniques need to be developed for 3D IC manufacturability and reliability. In particular, TSVs in 3D IC may cause significant thermal mechanical(More)
Low power is widely considered as a key benefit of 3D ICs, yet there have been few thorough design studies on how to maximize power benefits in 3D ICs. In this paper, we present design methodologies to reduce power consumption in 3D ICs using a large-scale commercial-grade microprocessor (OpenSPARC T2). To further improve power benefits in 3D ICs on top of(More)
— In this work, we study the through-silicon-via (TSV) RC variation impact on 3D power delivery network (PDN). First, we model TSV RC variation due to process variation. Then, we perform sign-off power supply noise analysis of 3D PDN in GDSII layouts which contain power/ground (P/G) TSV RC variation model. We explore the effect of TSV RC variation range,(More)
In this work, we propose an efficient and accurate full-chip through-silicon-via (TSV) interfacial crack analysis flow and design optimization methodology to alleviate TSV interfacial crack problems in 3D ICs. First, we analyze TSV interfacial crack at TSV/dielectric liner interface caused by TSV-induced thermo-mechanical stress. Then, we explore the impact(More)
We study the impact of material property variations in through-silicon-via (TSV) and its surrounding structures on the reliability and performance of 3D ICs. We focus on coefficient of thermal expansion (CTE) and Young's modulus variations for TSV, barrier, and liner materials. Our toolset efficiently handles the complexity of modeling and analysis of(More)
—In this paper, we propose a fast and accurate chip/package thermomechanical stress co-analysis tool for through-silicon-via (TSV)-based 3-D ICs. We use our tool for full-stack mechanical reliability as well as stress-aware timing analyses. First, we analyze the stress induced by chip/package intercon-explore and validate the principle of lateral and(More)