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Test compression

Test Compression is a technique used to reduce the time and cost of testing integrated circuits. The first ICs were tested with test vectors created… Expand
Wikipedia

Related topics

Related topics

5 relations
Design for testingElectronic design automationIntegrated circuitIntegrated circuit design

Broader (1)

Electronic engineering

Papers overview

Semantic Scholar uses AI to extract papers important to this topic.
2016
2016
Wavelet analysis to decompose a vibration simulation signal to improve pre-distribution testing of packaging
In general, vehicle vibration is non-stationary and has a non-Gaussian probability distribution; yet existing testing methods for… Expand
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2010
2010
X-Filling for Simultaneous Shift- and Capture-Power Reduction in At-Speed Scan-Based Testing
Power consumption during at-speed scan-based testing can be significantly higher than that during normal functional mode in both… Expand
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Highly Cited
2010
Highly Cited
2010
Test Data Compression Using Efficient Bitmask and Dictionary Selection Methods
  • K. Basu, P. Mishra
  • IEEE Transactions on Very Large Scale Integration…
  • 2010
    • Corpus ID: 16566420
Higher circuit densities in system-on-chip (SOC) designs have led to drastic increase in test data volume. Larger test data size… Expand
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2010
2010
Test Patterns Compression Technique Based on a Dedicated SAT-Based ATPG
In this paper we propose a new method of test patterns compression based on a design of a dedicated SAT-based ATPG (Automatic… Expand
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Highly Cited
2009
Highly Cited
2009
Low-Power Scan Operation in Test Compression Environment
This paper presents a new and comprehensive low-power test scheme compatible with a test compression environment. The key… Expand
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2007
2007
Test Cost Reduction for SoC Using a Combined Approach to Test Data Compression and Test Scheduling
A combined approach for implementing system level test compression and core test scheduling to reduce SoC test costs is proposed… Expand
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Highly Cited
2006
Highly Cited
2006
XPAND: an efficient test stimulus compression technique
Combinational circuits implemented with exclusive-or gates are used for on-chip generation of deterministic test patterns from… Expand
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Highly Cited
2005
Highly Cited
2005
RL-huffman encoding for test compression and power reduction in scan applications
This article mixes two encoding techniques to reduce test data volume, test pattern delivery time, and power dissipation in scan… Expand
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2004
2004
Fast, layout-aware validation of test-vectors for nanometer-related timing failures
ATPG tools generate test vectors assuming the zero delay model for logic gates. In reality, however, gates have finite rise and… Expand
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Highly Cited
1987
Highly Cited
1987
A Unified View of Test Compression Methods
A unified treatment of the various techniques to reduce the output data from a unit under test is given. The characteristics of… Expand
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