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In general, vehicle vibration is non-stationary and has a non-Gaussian probability distribution; yet existing testing methods for… Expand Power consumption during at-speed scan-based testing can be significantly higher than that during normal functional mode in both… Expand Higher circuit densities in system-on-chip (SOC) designs have led to drastic increase in test data volume. Larger test data size… Expand In this paper we propose a new method of test patterns compression based on a design of a dedicated SAT-based ATPG (Automatic… Expand This paper presents a new and comprehensive low-power test scheme compatible with a test compression environment. The key… Expand A combined approach for implementing system level test compression and core test scheduling to reduce SoC test costs is proposed… Expand Combinational circuits implemented with exclusive-or gates are used for on-chip generation of deterministic test patterns from… Expand This article mixes two encoding techniques to reduce test data volume, test pattern delivery time, and power dissipation in scan… Expand ATPG tools generate test vectors assuming the zero delay model for logic gates. In reality, however, gates have finite rise and… Expand A unified treatment of the various techniques to reduce the output data from a unit under test is given. The characteristics of… Expand