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Test compression
Test Compression is a technique used to reduce the time and cost of testing integrated circuits. The first ICs were tested with test vectors created…
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Related topics
Related topics
5 relations
Design for testing
Electronic design automation
Integrated circuit
Integrated circuit design
Broader (1)
Electronic engineering
Papers overview
Semantic Scholar uses AI to extract papers important to this topic.
2010
2010
Test Patterns Compression Technique Based on a Dedicated SAT-Based ATPG
Jiri Balcarek
,
P. Fišer
,
Jan Schmidt
13th Euromicro Conference on Digital System…
2010
Corpus ID: 2353727
In this paper we propose a new method of test patterns compression based on a design of a dedicated SAT-based ATPG (Automatic…
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2009
2009
Highly X-Tolerant Selective Compaction of Test Responses
Grzegorz Mrugalski
,
N. Mukherjee
,
J. Rajski
,
Dariusz Czysz
,
J. Tyszer
IEEE VLSI Test Symposium
2009
Corpus ID: 3641576
The paper presents a new scan chain selection scheme for response compaction. The proposed solution performs selective masking of…
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2009
2009
Integrated LFSR Reseeding, Test-Access Optimization, and Test Scheduling for Core-Based System-on-Chip
Zhanglei Wang
,
K. Chakrabarty
,
Seongmoon Wang
IEEE Transactions on Computer-Aided Design of…
2009
Corpus ID: 15235552
We present a system-on-chip (SOC) testing approach that integrates test data compression, test-access mechanism/test wrapper…
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2008
2008
VirtualScan: Test Compression Technology Using Combinational Logic and One-Pass ATPG
Laung-Terng Wang
,
X. Wen
,
+4 authors
Xinli Gu
IEEE Design & Test of Computers
2008
Corpus ID: 942699
IC testing based on a full-scan design methodology and ATPG is the most widely used test strategy today. However, rapidly growing…
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2007
2007
Test Cost Reduction for SoC Using a Combined Approach to Test Data Compression and Test Scheduling
Quming Zhou
,
K. J. Balakrishnan
Design, Automation & Test in Europe Conference…
2007
Corpus ID: 14154424
A combined approach for implementing system level test compression and core test scheduling to reduce SoC test costs is proposed…
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2006
2006
Test-Volume Reduction in Systems-on-a-Chip Using Heterogeneous and Multilevel Compression Techniques
L. Lingappan
,
S. Ravi
,
A. Raghunathan
,
N. Jha
,
S. Chakradhar
IEEE Transactions on Computer-Aided Design of…
2006
Corpus ID: 16037011
In this paper, the authors present compression techniques for effectively reducing the test-data-volume requirements of modern…
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2006
2006
Using Limited Dependence Sequential Expansion for Decompressing Test Vectors
Avijit Dutta
,
N. Touba
IEEE International Test Conference
2006
Corpus ID: 12640891
Existing techniques that incorporate decompressor constraints in the ATPG search/backtrace (e.g., Illinois scan) are based on…
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2006
2006
FCSCAN: an efficient multiscan-based test compression technique for test cost reduction
Youhua Shi
,
N. Togawa
,
S. Kimura
,
M. Yanagisawa
,
T. Ohtsuki
Asia and South Pacific Conference on Design…
2006
Corpus ID: 12735517
This paper proposes a new multiscan-based test input data compression technique by employing a fan-out compression scan…
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Highly Cited
2003
Highly Cited
2003
Test application time and volume compression through seed overlapping
Wenjing Rao
,
I. Bayraktaroglu
,
A. Orailoglu
Proceedings - Design Automation Conference
2003
Corpus ID: 6452057
We propose in this paper an extension on the Scan Chain Concealment technique to further reduce test time and volume requirement…
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Highly Cited
1987
Highly Cited
1987
A Unified View of Test Compression Methods
John P. Robinson
,
N. Saxena
IEEE transactions on computers
1987
Corpus ID: 5137854
A unified treatment of the various techniques to reduce the output data from a unit under test is given. The characteristics of…
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