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Test compression

Test Compression is a technique used to reduce the time and cost of testing integrated circuits. The first ICs were tested with test vectors created… Expand
Wikipedia

Related topics

Related topics

5 relations
Design for testingElectronic design automationIntegrated circuitIntegrated circuit design

Broader (1)

Electronic engineering

Papers overview

Semantic Scholar uses AI to extract papers important to this topic.
2016
2016
Wavelet analysis to decompose a vibration simulation signal to improve pre-distribution testing of packaging
In general, vehicle vibration is non-stationary and has a non-Gaussian probability distribution; yet existing testing methods for… Expand
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2011
2011
Power-aware test generation with guaranteed launch safety for at-speed scan testing
At-speed scan testing may suffer from severe yield loss due to the launch safety problem, where test responses are invalidated by… Expand
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2010
2010
X-Filling for Simultaneous Shift- and Capture-Power Reduction in At-Speed Scan-Based Testing
  • J. Li, Q. Xu, Y. Hu, X. Li
  • IEEE Transactions on Very Large Scale Integration…
  • 2010
    • Corpus ID: 6937712
Power consumption during at-speed scan-based testing can be significantly higher than that during normal functional mode in both… Expand
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2007
2007
Test Cost Reduction for SoC Using a Combined Approach to Test Data Compression and Test Scheduling
A combined approach for implementing system level test compression and core test scheduling to reduce SoC test costs is proposed… Expand
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Highly Cited
2006
Highly Cited
2006
XPAND: an efficient test stimulus compression technique
Combinational circuits implemented with exclusive-or gates are used for on-chip generation of deterministic test patterns from… Expand
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2006
2006
Using Limited Dependence Sequential Expansion for Decompressing Test Vectors
Existing techniques that incorporate decompressor constraints in the ATPG search/backtrace (e.g., Illinois scan) are based on… Expand
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2006
2006
Functional Constraints vs. Test Compression in Scan-Based Delay Testing
We present an approach to prevent over testing in scan-based delay test. The test data is transformed with respect to functional… Expand
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Highly Cited
2005
Highly Cited
2005
RL-huffman encoding for test compression and power reduction in scan applications
This article mixes two encoding techniques to reduce test data volume, test pattern delivery time, and power dissipation in scan… Expand
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2004
2004
Fast, layout-aware validation of test-vectors for nanometer-related timing failures
ATPG tools generate test vectors assuming the zero delay model for logic gates. In reality, however, gates have finite rise and… Expand
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Highly Cited
2003
Highly Cited
2003
Test application time and volume compression through seed overlapping
We propose in this paper an extension on the Scan Chain Concealment technique to further reduce test time and volume requirement… Expand
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