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Test compression

Test Compression is a technique used to reduce the time and cost of testing integrated circuits. The first ICs were tested with test vectors created… 
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Related topics

Related topics

5 relations
Design for testingElectronic design automationIntegrated circuitIntegrated circuit design

Broader (1)

Electronic engineering

Papers overview

Semantic Scholar uses AI to extract papers important to this topic.
Highly Cited
2017
Highly Cited
2017
Experimental and analytical evaluation of rubberized polymer concrete
2011
2011
Power-aware test generation with guaranteed launch safety for at-speed scan testing
At-speed scan testing may suffer from severe yield loss due to the launch safety problem, where test responses are invalidated by… 
2010
2010
X-Filling for Simultaneous Shift- and Capture-Power Reduction in At-Speed Scan-Based Testing
Power consumption during at-speed scan-based testing can be significantly higher than that during normal functional mode in both… 
Highly Cited
2006
Highly Cited
2006
XPAND: an efficient test stimulus compression technique
Combinational circuits implemented with exclusive-or gates are used for on-chip generation of deterministic test patterns from… 
Highly Cited
2006
Highly Cited
2006
Functional Constraints vs. Test Compression in Scan-Based Delay Testing
We present an approach to prevent overtesting in scan-based delay test. The test data is transformed with respect to functional… 
2006
2006
Increasing encoding efficiency of LFSR reseeding-based test compression
A new methodology to increase the encoding efficiency of test compression based on linear feedback shift registers (LFSRs) is… 
Highly Cited
2005
Highly Cited
2005
RL-huffman encoding for test compression and power reduction in scan applications
This article mixes two encoding techniques to reduce test data volume, test pattern delivery time, and power dissipation in scan… 
2004
2004
Fast, layout-aware validation of test-vectors for nanometer-related timing failures
ATPG tools generate test vectors assuming the zero delay model for logic gates. In reality, however, gates have finite rise and… 
Highly Cited
2003
Highly Cited
2003
Test application time and volume compression through seed overlapping
We propose in this paper an extension on the Scan Chain Concealment technique to further reduce test time and volume requirement… 
Highly Cited
1987
Highly Cited
1987
A Unified View of Test Compression Methods
A unified treatment of the various techniques to reduce the output data from a unit under test is given. The characteristics of… 
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