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Test compression

Test Compression is a technique used to reduce the time and cost of testing integrated circuits. The first ICs were tested with test vectors created… Expand
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Papers overview

Semantic Scholar uses AI to extract papers important to this topic.
2016
2016
In general, vehicle vibration is non-stationary and has a non-Gaussian probability distribution; yet existing testing methods for… Expand
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2010
2010
Power consumption during at-speed scan-based testing can be significantly higher than that during normal functional mode in both… Expand
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Highly Cited
2010
Highly Cited
2010
  • K. Basu, P. Mishra
  • IEEE Transactions on Very Large Scale Integration…
  • 2010
  • Corpus ID: 16566420
Higher circuit densities in system-on-chip (SOC) designs have led to drastic increase in test data volume. Larger test data size… Expand
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2010
2010
In this paper we propose a new method of test patterns compression based on a design of a dedicated SAT-based ATPG (Automatic… Expand
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Highly Cited
2009
Highly Cited
2009
This paper presents a new and comprehensive low-power test scheme compatible with a test compression environment. The key… Expand
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2007
2007
A combined approach for implementing system level test compression and core test scheduling to reduce SoC test costs is proposed… Expand
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Highly Cited
2006
Highly Cited
2006
Combinational circuits implemented with exclusive-or gates are used for on-chip generation of deterministic test patterns from… Expand
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Highly Cited
2005
Highly Cited
2005
This article mixes two encoding techniques to reduce test data volume, test pattern delivery time, and power dissipation in scan… Expand
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2004
2004
ATPG tools generate test vectors assuming the zero delay model for logic gates. In reality, however, gates have finite rise and… Expand
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Highly Cited
1987
Highly Cited
1987
A unified treatment of the various techniques to reduce the output data from a unit under test is given. The characteristics of… Expand
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