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Test compression

Test Compression is a technique used to reduce the time and cost of testing integrated circuits. The first ICs were tested with test vectors created… 
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Papers overview

Semantic Scholar uses AI to extract papers important to this topic.
2010
2010
In this paper we propose a new method of test patterns compression based on a design of a dedicated SAT-based ATPG (Automatic… 
2009
2009
The paper presents a new scan chain selection scheme for response compaction. The proposed solution performs selective masking of… 
2009
2009
We present a system-on-chip (SOC) testing approach that integrates test data compression, test-access mechanism/test wrapper… 
2008
2008
IC testing based on a full-scan design methodology and ATPG is the most widely used test strategy today. However, rapidly growing… 
2007
2007
A combined approach for implementing system level test compression and core test scheduling to reduce SoC test costs is proposed… 
2006
2006
In this paper, the authors present compression techniques for effectively reducing the test-data-volume requirements of modern… 
2006
2006
Existing techniques that incorporate decompressor constraints in the ATPG search/backtrace (e.g., Illinois scan) are based on… 
2006
2006
This paper proposes a new multiscan-based test input data compression technique by employing a fan-out compression scan… 
Highly Cited
2003
Highly Cited
2003
We propose in this paper an extension on the Scan Chain Concealment technique to further reduce test time and volume requirement… 
Highly Cited
1987
Highly Cited
1987
A unified treatment of the various techniques to reduce the output data from a unit under test is given. The characteristics of…