FAQ

Design for testing

Known as: DFT mode, Design For Test, Design for Testability 
Design for testing or design for testability (DFT) consists of IC design techniques that add testability features to a hardware product design. The… (More)
Wikipedia

Topic mentions per year

Topic mentions per year

1978-2016
05019782016

Related topics

Related topics

19 relations
Analog computerBuilt-in self-testClock signalComputational complexity theory
(More)

Related mentions per year

Related mentions per year

1942-2018
19401960198020002020
Design for testing
Computational complexity theory
Input/output
State space
Printed circuit board
Logic gate

Papers overview

Semantic Scholar uses AI to extract papers important to this topic.
Highly Cited
2005
Highly Cited
2005
Secure Scan: A Design-for-Test Architecture for Crypto Chips
Scan-based Design-for-Test (DFT) is a powerful testing scheme, but it can be used to retrieve the secrets stored in a crypto chip… (More)
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2003
2003
Layout-Driven SOC Test Architecture Design for Test Time and Wire Length Minimization
This paper extends existing SOC test architecture design approaches that minimize required tester vector memory depth and test… (More)
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Highly Cited
2000
Highly Cited
2000
Iddq testing for CMOS VLSI
It is little more than 15-years since the idea of Iddq testing was first proposed. Many semiconductor companies now consider Iddq… (More)
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2000
2000
Design for Testability – Test for Designability
  • Bob Neal
  • 2000
Designing for manufacturability and testability has been addressed by numerous publications and papers in the past. Some of the… (More)
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Highly Cited
1998
Highly Cited
1998
Scan chain design for test time reduction in core-based ICs
The size of the test vector set forms a significant factor in the overall production costs of ICs, as it defines the test… (More)
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Highly Cited
1997
Highly Cited
1997
Pentium® Pro Processor Design for Test and Debug
1 Its microarchitecture forms the basis of the company's future high-volume microprocessor portfolio. The initial design has also… (More)
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1996
1996
A design for testability technique for RTL circuits using control/data flow extraction
In this paper, we present a technique for extracting functional (control/data flow) information from register transfer level (RTL… (More)
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1996
1996
Weak Write Test Mode: An SRAM Cell Stability Design for Test Technique
The detection of cell stability and data retention faults in SRAMs has been a time consuminlg process. In this paper we discuss a… (More)
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Highly Cited
1994
Highly Cited
1994
Design for Testability in Object-Oriented Systems
estability is the relative ease and expense of revealing software faults. This article maps the testability terrain for object… (More)
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Highly Cited
1991
Highly Cited
1991
Design for Testability: Using Scanpath Techniques for Path-Delay Test and Measurement
2. Summary This paper presents techniques for using scanpath techniques in testing and measuring path-delays in a digital… (More)
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