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Design for testing
Known as:
Design For Test
, DFT
, Design for Testability
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Design for testing or design for testability (DFT) consists of IC design techniques that add testability features to a hardware product design. The…
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Related topics
Related topics
19 relations
Analog computer
Built-in self-test
Clock signal
Computational complexity theory
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Papers overview
Semantic Scholar uses AI to extract papers important to this topic.
Review
2002
Review
2002
Foundations of the X-machine Theory for Testing Research Report CS-02-06
A. J. Cowling
,
J. Aguado
2002
Corpus ID: 4676815
The X-machine (also known as Eilenberg X-machine) is an abstract model similar to the finite-state machine (FSM), which contains…
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2001
2001
Complete Functional Testing using Object Machines
Anthony J. H. Simons
,
K. Bogdanov
,
M. Holcombe
2001
Corpus ID: 18878850
Most software testing methods, even though they may detect some faults, can never finally assert whether the tested system is…
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1999
1999
Towards an architecture for reactive systems using an active real-time database and standardized components
A. Münnich
,
Marcel Birkhold
,
G. Färber
,
Peter Woitschach
Proceedings. IDEAS'99. International Database…
1999
Corpus ID: 14664545
Component-based concepts are being increasingly used in software design since they allow high-quality software to be generated…
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1999
1999
A study of some influencing factors in testability and diagnostics based on FSMs
K. Karoui
,
A. Ghedamsi
,
R. Dssouli
Proceedings IEEE International Symposium on…
1999
Corpus ID: 3229957
It is well known that the tests and diagnostics influence greatly communication software reliability. The testability and the…
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1996
1996
On minimizing the number of test points needed to achieve complete robust path delay fault testability
Prasanti Uppaluri
,
U. Sparmann
,
I. Pomeranz
Proceedings of 14th VLSI Test Symposium
1996
Corpus ID: 11010342
Recently, Pomeranz and Reddy (1994), presented a test point insertion method to improve path delay fault testability in large…
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1992
1992
Board test DFT model for computer products
Mick Tegethoff
,
T. Figal
,
S. Hird
Proceedings International Test Conference
1992
Corpus ID: 26256967
1. Abstract This paper describes a board test DFT model developed at HI? The model combines test effectiveness and board fault…
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1992
1992
Design for Testability Using Architectural Descriptions
V. Chickermane
,
Jaushin Lee
,
J. Patel
Proceedings International Test Conference
1992
Corpus ID: 35264755
This paper presents techniques to utilize high-level structural, functional and register-transjer information to perform design…
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Highly Cited
1992
Highly Cited
1992
A design for testability scheme to reduce test application time in full scan
D. Pradhan
,
J. Saxena
Digest of Papers. IEEE VLSI Test Symposium
1992
Corpus ID: 20875821
Full scan is a widely accepted design for testability technique for sequential circuits. However, the test application time…
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1990
1990
Digital Systems Testing and Design for Testability
M. Abramovici
,
M. Breuer
,
Allan D. Friedman
1990
Corpus ID: 59906080
3. Design for testability § Basic principles § Ad hoc solution, including test point insertion. § Scan techniques, theory and…
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1989
1989
Concurrent test generation and design for testability
K. Cheng
,
V. Agrawal
IEEE International Symposium on Circuits and…
1989
Corpus ID: 60831606
Results of test generation for sequential benchmark circuits are presented. Tests were generated by a concurrent test generation…
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