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Built-in self-test

Known as: Bit (disambiguation), Built-in, Bist 
A built-in self-test (BIST) or built-in test (BIT) is a mechanism that permits a machine to test itself. Engineers design BISTs to meet requirements… Expand
Wikipedia

Papers overview

Semantic Scholar uses AI to extract papers important to this topic.
Highly Cited
2010
Highly Cited
2010
A graphene-based photodetector with unprecedented photoresponsivity and the ability to perform error-free detection of 10 Gbit s… Expand
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Highly Cited
2007
Highly Cited
2007
In this paper, we propose a new programmable deterministic built-in self-Test (BIST) method that requires significantly lower… Expand
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Highly Cited
2004
Highly Cited
2004
Conjugated polymers are attractive semiconductors for photovoltaic cells because they are strong absorbers and can be deposited… Expand
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Highly Cited
1998
Highly Cited
1998
We introduce the first BIST approach for testing the programmable routing network in FPGAs. Our method detects opens in, and… Expand
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Highly Cited
1997
Highly Cited
1997
1. Built-In Self-Test. Introduction. Design for Testability. Generation of Test Vectors. Compaction of Test Responses. BIST… Expand
1997
1997
  • O. Petlin, S. Furber
  • Proceedings Third International Symposium on…
  • 1997
  • Corpus ID: 12992582
An asynchronous ARM6 microprocessor (AMULET1), designed at the University of Manchester using a two-phase signalling protocol… Expand
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Highly Cited
1992
Highly Cited
1992
The Weighted Histogram Analysis Method (WHAM), an extension of Ferrenberg and Swendsen's Multiple Histogram Technique, has been… Expand
Highly Cited
1989
Highly Cited
1989
A variation on a built-in self-test technique is presented that is based on a distributed pseudorandom number generator derived… Expand
Review
1985
Review
1985
  • E. McCluskey
  • IEEE Design & Test of Computers
  • 1985
  • Corpus ID: 20949409
A system that includes self-test features must have facilities for generating test patterns and analyzing the resultant circuit… Expand
Highly Cited
1984
Highly Cited
1984
A built-in self-test technique utilizing on-chip pseudorandom-pattern generation, on-chip signature analysis, a ``boundary scan… Expand
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