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Built-In Test for Circuits with Scan Based on Reseeding of Multiple-Polynomial Linear Feedback Shift Registers
- S. Hellebrand, J. Rajski, S. Tarnick, S. Venkataraman, B. Courtois
- Computer ScienceIEEE Trans. Computers
- 1 February 1995
A new scheme for built-in test that uses multiple-polynomial linear feedback shift registers (MP-LFSR's) and an implicit polynomial identification reduces the number of extra bits per seed to one bit is presented.
Strongly Code Disjoint Checkers
Strongly code-disjoint (SCD) checkers are defined and shown to include totally self-checking (TSC) code- Disjoint checkers, the largest class of checkers with which a combinational system may achieve the TSC goal.
GENERATION OF VECTOR PATTERNS THROUGH RESEEDING OF
This paper proposes a new BIST scheme where the generator can operate according to a number of primitive polynomials, and presents models of the encoding efficiency of this scheme, essentially preserving the conz- putational simplicity of single reseeding.
New ISFET sensor interface circuit for biomedical applications
Generation of Vector Patterns Through Reseeding of Multipe-Polynominal Linear Feedback Shift Registers
This paper proposes a new BIST scheme where the generator can operate according to a number of primitive polynomials and presents models of the encoding efficiency of this scheme and concludes that such a scheme with 16 polynmials approaches the efficiency of the scheme based on full poly- nomial programmability, essentially preserving theComputational simplicity of single reseeding.
Generation of Electrically Induced Stimuli for MEMS Self-Test
This work describes, for different types of MEMS, how the required non-electrical test stimuli can be induced on-chip by means of electrical signals, which provides the basis for adding BIST strategies for MEMS parts embedded in the coming generation of integrated systems.
Extending Fault-Based Testing to Microelectromechanical Systems
This paper illustrates how fault-based testing can be extended to MEMS, both for bulk and surface micromachining technologies, making possible the reuse of analog testing techniques.
A Reliable Fail-Safe System
The main contributions of this work rely on the fail safe/strongly fail safe design of the error masking interface, and on the analysis of the competitiveness of this fault tolerant scheme with respect to its reliability.
Fault simulation of MEMS using HDLs
- B. Charlot, S. Mir, É. Cota, M. Lubaszewski, B. Courtois
- EngineeringDesign, Test, Integration, and Packaging of MEMS…
- 10 March 1999
An approach to fault simulation of MEMS using an analog Hardware Description Language (HDL) which appears to be more comprehensive and systematic than previous approaches is described.