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The paper presents a novel low power test scheme integrated with the embedded deterministic test environment. It reduces significantly switching rates in scan chains with minimal hardware modification. Experimental results obtained for industrial circuits clearly indicate that switching activity can be reduced up to 150 times along with improved compression(More)
—The presented compression scheme is a novel solution that is based on deterministic vector clustering and encompasses three data reduction features in one on-chip decoding system. The approach preserves all benefits of continuous flow decompression and offers compression ratios of order 1000x with encoding efficiency much higher than 1.00. 1. Introduction(More)