Statistical static timing analysis
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We explore the implementation of Monte Carlo based statistical static timing analysis (SSTA) on a Graphics Processing Unit (GPU… Expand As the device and interconnect physical dimensions decrease steadily in modern nanometer silicon technologies, the ability to… Expand Static-timing analysis (STA) has been one of the most pervasive and successful analysis engines in the design of digital circuits… Expand Increasing process variation in the nanometer regime motivates the use of statistical static timing analysis tools for timing… Expand With CMOS technology scaling down to the nanometer realm, process variations have been increased. In particular, the increase of… Expand Existing statistical static timing analysis (SSTA) techniques suffer from limited modeling capability by using a linear delay… Expand As technology continues to advance deeper into the nanometer regime, a tight control on the process parameters is increasingly… Expand The ability to account for the growing impacts of multiple process variations in modern technologies is becoming an integral part… Expand With an increasing trend in the variation of the primary parameters affecting circuit performance, the need for statistical… Expand In this paper, we propose a new sensitivity based, statistical gate sizing method. Since circuit optimization effects the entire… Expand