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Delay calculation

Delay calculation is the term used in integrated circuit design for the calculation of the gate delay of a single logic gate and the wires attached… 
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Related topics

Related topics

17 relations
Asynchronous systemElectronic design automationElmore delayIntegrated circuit design

Papers overview

Semantic Scholar uses AI to extract papers important to this topic.
Highly Cited
2012
Highly Cited
2012
QPRD: QoS-aware Peering Routing Protocol for Delay Sensitive Data in Hospital Body Area Network Communication
The consistent performance, energy efficiency, and reliability are important factors for real-time monitoring of a patient's data… 
2008
2008
Implementation of Basic Arithmetic Operations Using Cellular Automaton
This paper presents hardware architecture to perform the basic arithmetic operation addition using cellular automata (CA). This… 
Highly Cited
2002
Highly Cited
2002
Test power reduction through minimization of scan chain transitions
Parallel test application helps reduce the otherwise considerable test times in SOCs; yet its applicability is limited by average… 
Review
2002
Review
2002
On-chip inductance cons and pros
  • Y. Ismail
  • IEEE Transactions on Very Large Scale Integration…
  • 2002
  • Corpus ID: 6560683
Provides a high level survey of the increasing effects of on-chip inductance. These effects are classified into desirable and… 
Highly Cited
2002
Highly Cited
2002
Gate sizing using Lagrangian relaxation combined with a fast gradient-based pre-processing step
In this paper, we present Forge, an optimal algorithm for gate sizing using the Elmore delay model. The algorithm utilizes… 
1997
1997
Timing analysis for extended burst-mode circuits
We describe an efficient timing analysis technique for extended burst-mode circuits implemented according to the 3D design style… 
Highly Cited
1997
Highly Cited
1997
Dynamic internal testing of CMOS circuits using hot luminescence
Subnanosecond pulses of hot electron luminescence are shown to be generated coincident with logic state switching of individual… 
Highly Cited
1994
Highly Cited
1994
VLSI architectures for computing exponentiations, multiplicative inverses, and divisions in GF(2/sup m/)
A systolic power-sum circuit designed to perform AB/sup 2/+C computation in the finite field GF(2/sup m/) has been presented… 
1992
1992
Statistical timing analysis of combinational circuits
The authors develop efficient methods for computing an exact probability distribution of the delay of a combinational circuit… 
1992
1992
A Highly Parallel FPL-Based Machine and Its Formal Verification
The SPACE machine is introduced as a new type of computer architecture, capable of very fast simulation of highly concurrent… 
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