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Delay calculation
Delay calculation is the term used in integrated circuit design for the calculation of the gate delay of a single logic gate and the wires attached…
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Related topics
Related topics
17 relations
Asynchronous system
Electronic design automation
Elmore delay
Integrated circuit design
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Papers overview
Semantic Scholar uses AI to extract papers important to this topic.
2008
2008
Implementation of Basic Arithmetic Operations Using Cellular Automaton
P. Choudhury
,
Sudhakar Sahoo
,
Mithun Chakraborty
International Conference on Information…
2008
Corpus ID: 40131201
This paper presents hardware architecture to perform the basic arithmetic operation addition using cellular automata (CA). This…
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Highly Cited
2002
Highly Cited
2002
Test power reduction through minimization of scan chain transitions
O. Sinanoglu
,
I. Bayraktaroglu
,
A. Orailoglu
Proceedings 20th IEEE VLSI Test Symposium (VTS )
2002
Corpus ID: 7131991
Parallel test application helps reduce the otherwise considerable test times in SOCs; yet its applicability is limited by average…
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Highly Cited
2002
Highly Cited
2002
Gate sizing using Lagrangian relaxation combined with a fast gradient-based pre-processing step
Hiran Tennakoon
,
C. Sechen
IEEE/ACM International Conference on Computer…
2002
Corpus ID: 53244448
In this paper, we present Forge, an optimal algorithm for gate sizing using the Elmore delay model. The algorithm utilizes…
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Review
2002
Review
2002
On-chip inductance cons and pros
Y. Ismail
IEEE Transactions on Very Large Scale Integration…
2002
Corpus ID: 6560683
Provides a high level survey of the increasing effects of on-chip inductance. These effects are classified into desirable and…
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Highly Cited
1997
Highly Cited
1997
Dynamic internal testing of CMOS circuits using hot luminescence
J. Kash
,
J. Tsang
IEEE Electron Device Letters
1997
Corpus ID: 1288809
Subnanosecond pulses of hot electron luminescence are shown to be generated coincident with logic state switching of individual…
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1997
1997
Timing analysis for extended burst-mode circuits
Supratik Chakraborty
,
D. Dill
,
Kun-Yung Chang
,
K. Yun
Proceedings Third International Symposium on…
1997
Corpus ID: 16723552
We describe an efficient timing analysis technique for extended burst-mode circuits implemented according to the 3D design style…
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1997
1997
A roadmap of CAD tool changes for sub-micron interconnect problems
L. Scheffer
ACM International Symposium on Physical Design
1997
Corpus ID: 10029855
Correct interconnect design is crucial to making sub-micron chips that work. Right now CAD tools do little or nothing to help…
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1992
1992
A Highly Parallel FPL-Based Machine and Its Formal Verification
Paul Shaw
,
G. Milne
International Conference on Field-Programmable…
1992
Corpus ID: 5490138
The SPACE machine is introduced as a new type of computer architecture, capable of very fast simulation of highly concurrent…
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1989
1989
Logic decomposition algorithms for the timing optimization of multi-level logic
P. Paulin
,
F. Poirot
Proceedings IEEE International Conference on…
1989
Corpus ID: 62401546
Novel fast decomposition algorithms that rely on precise linear models for gate delays are presented. Within the limits of the…
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1979
1979
Minimum Parallel Binary Adders with NOR (NAND) Gates
H. Lai
,
S. Muroga
IEEE transactions on computers
1979
Corpus ID: 23026844
Parallel binary adders of n bits long in single-rail input logic which have a minimum number of NOR gates are derived in this…
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