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Delay calculation

Delay calculation is the term used in integrated circuit design for the calculation of the gate delay of a single logic gate and the wires attached… 
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Related topics

17 relations
Asynchronous systemElectronic design automationElmore delayIntegrated circuit design

Papers overview

Semantic Scholar uses AI to extract papers important to this topic.
2010
2010
NIM- a noise index model to estimate delay discrepancies between silicon and simulation
As CMOS technology continues to scale, the accurate prediction of silicon timing through the use of pre-silicon modeling and… 
2009
2009
Advanced Dynamic Source Routing with QoS Guarantee
With a great deal of different applications increasing, it needs to provide effect communication for mobile Ad Hoc network. In… 
2009
2009
Compact Delay Test Generation with a Realistic Low Cost Fault Coverage Metric
This paper proposes a realistic low cost fault coverage metric targeting both global and local delay faults. It suggests the test… 
2007
2007
Merge Logic for Clustered Multithreaded VLIW Processors
Clustered VLIW embedded processors have become widespread due to benefits of simple hardware and low power. Simultaneous… 
Highly Cited
2005
Highly Cited
2005
A new method for design of robust digital circuits
As technology continues to scale beyond 100 nm, there is a significant increase in performance uncertainty of CMOS logic due to… 
2004
2004
False aggressors pruning using path sensitization and logic implications
Coupled line switching can contribute to a large portion of the delay as well as the functionality of a circuit. In order to fix… 
2002
2002
Checking delay-insensitivity: 10/sup 4/ gates and beyond
Wire and gate delays are accounted to have equal, or nearly equal, effect on circuit behavior in modern design techniques. This… 
2002
2002
Measurement and Evaluation of Artificial Dielectric Material
Abstract : This report describes measurements of dielectric parameters for artificial dielectric materials using picosecond time… 
1997
1997
Timing analysis for extended burst-mode circuits
We describe an efficient timing analysis technique for extended burst-mode circuits implemented according to the 3D design style… 
1994
1994
Predicting circuit performance using circuit-level statistical timing analysis
Recognizing that the delay of a circuit is extremely sensitive to manufacturing process variations, this paper proposes a…