Delay calculation

Delay calculation is the term used in integrated circuit design for the calculation of the gate delay of a single logic gate and the wires attached… (More)
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2012
2012
As the device geometries are shrinking, the impact of crosstalk effects increases, which results in a stronger dependence of… (More)
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Highly Cited
2004
Highly Cited
2004
An efficient statistical timing analysis algorithm that can handle arbitrary (spatial and structural) causes of delay correlation… (More)
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2001
2001
Inferenceof network internallink characteristicshasbecomeanincreasinglyimportantissuefor operatingandevaluatinglarge… (More)
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Highly Cited
2000
Highly Cited
2000
In coupling delay computation, a Miller factor of more than 2X may be necessary to account for active coupling capacitance when… (More)
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Highly Cited
2000
Highly Cited
2000
Several architectures have been recently proposed to support IP mobility. Most studies, however, show that current protocols, in… (More)
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2000
2000
Efficient and accurate delay calculation is very important in physical design, optimization and fast verification. In this paper… (More)
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Highly Cited
1998
Highly Cited
1998
Increases in delay due to coupling can have a dramatic impact on IC performance for deep submicron technologies. To achieve… (More)
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Highly Cited
1997
Highly Cited
1997
This paper discusses a statistical approach to static timing analysis. Delays of gates and wires are modeled by stochastic values… (More)
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Highly Cited
1987
Highly Cited
1987
Techniques are developed in this dissertation to efficiently evaluate direct-mapped and set-associative caches. These techniques… (More)
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Highly Cited
1985
Highly Cited
1985
Delay testing of combinational logic in a clocked environment is analyzed. A model based upon paths is introduced for delay… (More)
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