Minimum Parallel Binary Adders with NOR (NAND) Gates

@article{Lai1979MinimumPB,
  title={Minimum Parallel Binary Adders with NOR (NAND) Gates},
  author={H. C. Lai and S. Muroga},
  journal={IEEE Transactions on Computers},
  year={1979},
  volume={C-28},
  pages={648-659}
}
  • H. C. Lai, S. Muroga
  • Published 1979
  • Mathematics, Computer Science
  • IEEE Transactions on Computers
  • Parallel binary adders of n bits long in single-rail input logic which have a minimum number of NOR gates are derived in this paper. The minimality of the number of NOR gates is proved for an arbitrary value of n. Also, it is proved that the adders must be a cascade of basic modules and that there exist many different types of basic modules. These adders have fewer gates and shorter net gate delays (or fewer connections) than the widely used carry-ripple adders which are a cascade of one-bit… CONTINUE READING
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