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Efficient and effective placement for very large circuits
  • W. Sun, C. Sechen
  • Computer Science
  • IEEE Trans. Comput. Aided Des. Integr. Circuits…
  • 7 November 1993
TLDR
A new hierarchical annealing-based placement program which yields total wire length reductions of up to 9% while consuming up to 7.5 times less CPU time in comparison to TimberWolfSC v6.0. Expand
VLSI Placement and Global Routing Using Simulated Annealing
TLDR
This paper presents a new approach to Cell-Based Placement and Global Routing of Standard Cell Integrated Circuits and discusses the TimberWolfMC pin site methodology, which automates the very labor-intensive and therefore time-heavy process of cell placement and routing. Expand
The TimberWolf placement and routing package
TLDR
TimberWolf is an integrated set of placement and routing optimization programs for standard cell, macro/custom cell, and gate-array placement, as well as standard cell global routing. Expand
TimberWolf3.2: A New Standard Cell Placement and Global Routing Package
TLDR
Local changes are made to the placement whenever such changes result in a reduction in the number of wiring tracks required, and TimberWolf3.2 has achieved area savings ranging from 15 to 75% in experiments on numerous industrial circuits. Expand
Timing Driven Placement for Large Standard Cell Circuits
TLDR
The timing optimization algorithm has been added to the placement algorithm which has yielded the best results ever reported on the full set of MCNC benchmark circuits, including a circuit containing more than 100,000 cells. Expand
Efficient and effective placement for very large circuits
TLDR
Two major extensions to the implementation of simulated annealing for row-based placement are presented which have enabled it to obtain the best results ever reported for a large set of MCNC benchmark circuits while using the least computation timeEver reported for remotely comparable results. Expand
Gate sizing using Lagrangian relaxation combined with a fast gradient-based pre-processing step
TLDR
The Forge algorithm, an optimal algorithm for gate sizing using the Elmore delay model, is presented, which utilizes Lagrangian relaxation with a fast gradient-based pre-processing step that provides an effective set of initial Lagrange multipliers. Expand
A MEMS-Assisted Temperature Sensor With 20- μK Resolution, Conversion Rate of 200 S/s, and FOM of 0.04 pJK2
TLDR
A dual-microelectromechanical system (MEMS) resonator-based temperature sensor that enables us to implement a MEMS-based programmable oscillator with an Allan deviation of <;1e-10 over 1 s averaging time, and a frequency stability of<;±0.1 parts per million in the temperature range from -45 °C to 105 °C. Expand
A unified approach to the approximate symbolic analysis of large analog integrated circuits
TLDR
A unified approach to the approximate symbolic analysis of large linearized analog circuits in the complex frequency domain, which combines two new approximation-during-computation strategies with a variation of the classical two-graph tree enumeration method to symbolically analyze much larger analog integrated circuits than previously reported. Expand
A new global router for row-based layout
  • Kai-Win Lee, C. Sechen
  • Engineering, Computer Science
  • [] IEEE International Conference on Computer…
  • 7 November 1988
TLDR
A global router for row-based layout styles such as sea-of-gates, gate-array, and standard cell circuits is discussed, generalized to handle macro blocks on the chip, equivalent sets of pins, single pins (those without an equivalent), and circuits having many or no built-into-the-cell feeds. Expand
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