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- Publications
- Influence

A Theory of Timed Automata

Alur, R. and D.L. Dill, A theory of timed automata, Theoretical Computer Science 126 (1994) 183-235. We propose timed (j&e) automata to model the behavior of real-time systems over time. Our… Expand

Model-Checking in Dense Real-time

- R. Alur, C. Courcoubetis, D. Dill
- Computer Science
- Inf. Comput.
- 1 May 1993

Model-checking is a method of verifying concurrent systems in which a state-transition graph model of the system behavior is compared with a temporal logic formula. This paper extends model-checking… Expand

EXE: Automatically Generating Inputs of Death

- Cristian Cadar, Vijay Ganesh, Peter M. Pawlowski, D. Dill, D. Engler
- Computer Science
- TSEC
- 1 December 2008

This article presents EXE, an effective bug-finding tool that automatically generates inputs that crash real code. Instead of running code on manually or randomly constructed input, EXE runs it on… Expand

Hwang: Symbolic Model Checking: 1020 states and beyond

- J. Burch, E. Clarke, K. McMillan, D. Dill
- Computer Science
- 1992

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- 103

Reluplex: An Efficient SMT Solver for Verifying Deep Neural Networks

- G. Katz, C. Barrett, D. Dill, Kyle Julian, Mykel J. Kochenderfer
- Computer Science
- CAV
- 3 February 2017

Deep neural networks have emerged as a widely used and effective means for tackling complex, real-world problems. However, a major obstacle in applying them to safety-critical systems is the great… Expand

Automata For Modeling Real-Time Systems

To model the behavior of finite-state asynchronous real-time systems we propose the notion of timed Buchi automata (TBA). TBAs are Buchi automata coupled with a mechanism to express constant bounds… Expand

Timing Assumptions and Verification of Finite-State Concurrent Systems

- D. Dill
- Computer Science
- Automatic Verification Methods for Finite State…
- 12 June 1989

We have described a scheme that allows timing assumptions to be incorporated into automatic proofs of arbitrary finite-state temporal properties. The obvious extension is to be able to prove timing… Expand

A Decision Procedure for Bit-Vectors and Arrays

- Vijay Ganesh, D. Dill
- Computer Science
- CAV
- 3 July 2007

STP is a decision procedure for the satisfiability of quantifier-free formulas in the theory of bit-vectors and arrays that has been optimized for large problems encountered in software analysis… Expand

Trace theory for automatic hierarchical verification of speed-independent circuits

- D. Dill
- Computer Science
- ACM distinguished dissertations
- 7 September 1989

A theory of automatic hierarchical verification of speed-independent circuits is developed and implemented. The theory models circuits as trace structures. Trace structures represent the behaviors of… Expand

Symbolic Model Checking: 10^20 States and Beyond

- J. Burch, E. Clarke, K. McMillan, D. Dill, L. Hwang
- Computer Science, Mathematics
- Inf. Comput.
- 4 June 1990

A general method that represents the state space symbolically instead of explicitly is described. The generality of the method comes from using a dialect of the mu-calculus as the primary… Expand