Ulf Schlichtmann

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Standard cell circuits consist of millions of standard cells, which have to be aligned overlap-free to the rows of the chip. Placement of these circuits is done in consecutive steps. First, a global placement is obtained by roughly spreading the cells on the chip, while considering all relevant objectives like wirelength, and routability. After that, the(More)
The analog placement algorithm <i>Plantage</i>, presented in this paper, generates placements for analog circuits with comprehensive placement constraints. Plantage is based on a hierarchically bounded enumeration of basic building blocks, using B*-trees. The practically relevant solution space is thereby enumerated quasi-complete. The sets of possible(More)
A new net scheduling and allocation model generates net schedules that minimize either execution time or resources. The author tested the model within a VHDL-based high-level synthesis system called Ahiles. Alternative graphs provide an efficient, uniform model describing the structure, functions, and faults in a wide class of digital circuits and for(More)
We present an aging analysis flow able to calculate the degraded circuit timing. To the best of our knowledge it is the first approach on gate level so far capable of analyzing the impact of the two dominant drift-related aging effects – NBTI and HCI – on complex digital circuits. The aging-aware gate model used to compute the aged circuit timing provides(More)
This paper introduces a new architecture for circuit-based Physical Unclonable Functions (PUFs) which we call the Bistable Ring PUF (BR-PUF). Based on experimental results obtained from FPGA-based implementations of the BR-PUF, the quality of this new design is discussed in different aspects, including uniqueness and reliability. On the basis of the(More)
This paper presents the sizing rules method for basic building blocks in analog CMOS and bipolar circuit design. It consists of the development of a hierarchical library of transistor-pair groups as basic building blocks for analog CMOS and bipolar circuits, the derivation of a hierarchical generic list of constraints that must be satisfied to guarantee the(More)
This paper introduces chamcteristic signatures for Boolean functions. The signatures do not ezhibit sensitivity to permutations of input vtrn”ables. We use these signatures to develop a method of rapidly matching subcircuits with cells in a (large) library. The procedure is analogous to hashing. This approach promises significant improvements for tibrary(More)
In this paper, a hierarchical optimization methodology for charge pump phase-locked loops (CPPLLs) is proposed. It has the following features: 1) A comprehensive and efficient behavioral modeling of the PLL enables fast simulations and includes the important PLL performances jitter, power and locking time, as well as stability constraints for the nonlinear(More)