FAQ

Shallow trench isolation

Known as: Box Isolation Technique 
Shallow trench isolation (STI), also known as box isolation technique, is an integrated circuit feature which prevents electric current leakage… (More)
Wikipedia

Topic mentions per year

Topic mentions per year

1984-2017
010203019842017

Related topics

Related topics

10 relations
CMOSChemical-mechanical planarizationClock feedthroughEtching
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Broader (1)

Semiconductor device fabrication

Related mentions per year

Related mentions per year

1937-2018
19401960198020002020
Shallow trench isolation
CMOS
Semiconductor device fabrication
Integrated circuit
Etching
Semiconductor device

Papers overview

Semantic Scholar uses AI to extract papers important to this topic.
2011
2011
Modeling Low Dose Rate Effects in Shallow Trench Isolation Oxides
Low dose rate experiments on field-oxide-field-effect-transistors (FOXFETs) fabricated in a 90 nm CMOS technology indicate that… (More)
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2010
2010
Low Dose Rate Effects in Shallow Trench Isolation Regions
Dose-rate effects are studied in shallow trench isolation regions. Increased damage is observed at low dose rate, with a… (More)
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2006
2006
Fill for Shallow Trench Isolation CMP
Shallow trench isolation (STI) is the mainstream CMOS isolation technology. It uses chemical mechanical polishing (CMP) to remove… (More)
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Highly Cited
2004
Highly Cited
2004
Nonuniform total-dose-induced charge distribution in shallow-trench isolation oxides
A new approach for modeling the radiation-induced charge distribution in shallow-trench isolation (STI) structures shows that… (More)
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2003
2003
Electrical analysis of mechanical stress induced by shallow trench isolation [MOSFETs]
This paper presents an electrical analysis of mechanical stress induced by shallow trench isolation (STI) on MOSFETs of advanced… (More)
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2002
2002
Issues in Shallow Trench Isolation CMP
As advancing technologies increase the demand for planarity in integrated circuits, nanotopography has emerged as an important… (More)
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2002
2002
Modeling of chemical mechanical polishing for shallow trench isolation
Chemical mechanical polishing (CMP) is a key process enabling shallow trench isolation (STI), which is used in current integrated… (More)
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Review
1998
Review
1998
Shallow trench isolation for advanced ULSI CMOS technologies
This paper reviews the requirements and challenges in designing a Shallow Trench Isolation (STI) process flow for 0.1 /spl mu/m… (More)
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1996
1996
A novel 0.25 /spl mu/m shallow trench isolation technology
A novel shallow trench isolation technology has been proposed for 0.25 /spl mu/m CMOS VLSI applications. The gate oxide and a… (More)
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1985
1985
Latchup-free CMOS structure using shallow trench isolation
Using a shallow trench and a thin epitaxial layer, latchup-free CMOS has been realized. When the trench depth is 1.4 µm and… (More)
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