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Shallow trench isolation
Known as:
Box Isolation Technique
Â
Shallow trench isolation (STI), also known as box isolation technique, is an integrated circuit feature which prevents electric current leakage…Â
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Wikipedia
Topic mentions per year
Topic mentions per year
1984-2017
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1984
2017
Related topics
Related topics
10 relations
CMOS
Chemical-mechanical planarization
Clock feedthrough
Etching
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Broader (1)
Semiconductor device fabrication
Related mentions per year
Related mentions per year
1937-2018
1940
1960
1980
2000
2020
Shallow trench isolation
CMOS
Semiconductor device fabrication
Integrated circuit
Etching
Semiconductor device
Papers overview
Semantic Scholar uses AI to extract papers important to this topic.
2011
2011
Modeling Low Dose Rate Effects in Shallow Trench Isolation Oxides
I. S. Esqueda
,
H. J. Barnaby
,
+4 authors
R. L. Pease
IEEE Transactions on Nuclear Science
2011
Low dose rate experiments on field-oxide-field-effect-transistors (FOXFETs) fabricated in a 90 nm CMOS technology indicate that…Â
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2010
2010
Low Dose Rate Effects in Shallow Trench Isolation Regions
A. H. Johnston
,
R. T. Swimm
,
T. F. Miyahira
IEEE Transactions on Nuclear Science
2010
Dose-rate effects are studied in shallow trench isolation regions. Increased damage is observed at low dose rate, with a…Â
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2006
2006
Fill for Shallow Trench Isolation CMP
Andrew B. Kahng
,
Puneet Sharma
,
Alex Zelikovsky
2006 IEEE/ACM International Conference on…
2006
Shallow trench isolation (STI) is the mainstream CMOS isolation technology. It uses chemical mechanical polishing (CMP) to remove…Â
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Highly Cited
2004
Highly Cited
2004
Nonuniform total-dose-induced charge distribution in shallow-trench isolation oxides
Marek Turowski
,
A. Raman
,
R. D. Schrimpf
IEEE Transactions on Nuclear Science
2004
A new approach for modeling the radiation-induced charge distribution in shallow-trench isolation (STI) structures shows that…Â
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2003
2003
Electrical analysis of mechanical stress induced by shallow trench isolation [MOSFETs]
C. Gallon
,
G. Reimbold
,
Giovanni Ghibaudo
,
R. Blanchi
,
Romain Gwoziecki
,
C. Raynaud
ESSDERC '03. 33rd Conference on European Solid…
2003
This paper presents an electrical analysis of mechanical stress induced by shallow trench isolation (STI) on MOSFETs of advanced…Â
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2002
2002
Issues in Shallow Trench Isolation CMP
Duane S. Boning
,
Brian Lee
2002
As advancing technologies increase the demand for planarity in integrated circuits, nanotopography has emerged as an important…Â
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2002
2002
Modeling of chemical mechanical polishing for shallow trench isolation
Brian Lee
2002
Chemical mechanical polishing (CMP) is a key process enabling shallow trench isolation (STI), which is used in current integrated…Â
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Review
1998
Review
1998
Shallow trench isolation for advanced ULSI CMOS technologies
M. Nandakumar
,
A. Chatterjee
,
S. Sridhar
,
Kate Joyner
,
Mark S. Rodder
,
I.-C. Chen
International Electron Devices Meeting 1998…
1998
This paper reviews the requirements and challenges in designing a Shallow Trench Isolation (STI) process flow for 0.1 /spl mu/m…Â
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1996
1996
A novel 0.25 /spl mu/m shallow trench isolation technology
C. Chen
,
J W Chou
,
W. Lur
,
S Sun
International Electron Devices Meeting. Technical…
1996
A novel shallow trench isolation technology has been proposed for 0.25 /spl mu/m CMOS VLSI applications. The gate oxide and a…Â
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1985
1985
Latchup-free CMOS structure using shallow trench isolation
Yoichi Niitsu
,
Susumu Taguchi
,
+4 authors
Keita Kanzaki
1985 International Electron Devices Meeting
1985
Using a shallow trench and a thin epitaxial layer, latchup-free CMOS has been realized. When the trench depth is 1.4 µm and…Â
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