Shallow trench isolation

Known as: Box Isolation Technique 
Shallow trench isolation (STI), also known as box isolation technique, is an integrated circuit feature which prevents electric current leakage… (More)
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Topic mentions per year

Topic mentions per year

1984-2017
010203019842017

Papers overview

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2011
2011
Low dose rate experiments on field-oxide-field-effect-transistors (FOXFETs) fabricated in a 90 nm CMOS technology indicate that… (More)
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2010
2010
Dose-rate effects are studied in shallow trench isolation regions. Increased damage is observed at low dose rate, with a… (More)
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2006
2006
Shallow trench isolation (STI) is the mainstream CMOS isolation technology. It uses chemical mechanical polishing (CMP) to remove… (More)
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Highly Cited
2004
Highly Cited
2004
A new approach for modeling the radiation-induced charge distribution in shallow-trench isolation (STI) structures shows that… (More)
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2003
2003
This paper presents an electrical analysis of mechanical stress induced by shallow trench isolation (STI) on MOSFETs of advanced… (More)
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2002
2002
As advancing technologies increase the demand for planarity in integrated circuits, nanotopography has emerged as an important… (More)
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2002
2002
Chemical mechanical polishing (CMP) is a key process enabling shallow trench isolation (STI), which is used in current integrated… (More)
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Review
1998
Review
1998
This paper reviews the requirements and challenges in designing a Shallow Trench Isolation (STI) process flow for 0.1 /spl mu/m… (More)
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1996
1996
A novel shallow trench isolation technology has been proposed for 0.25 /spl mu/m CMOS VLSI applications. The gate oxide and a… (More)
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1985
1985
Using a shallow trench and a thin epitaxial layer, latchup-free CMOS has been realized. When the trench depth is 1.4 µm and… (More)
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