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Salicide
The term salicide refers to a technology used in the microelectronics industry used to form electrical contacts between the semiconductor device and…
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Related topics
Related topics
7 relations
Etching (microfabrication)
Polycide
Semiconductor
Semiconductor device
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Broader (1)
Semiconductor device fabrication
Papers overview
Semantic Scholar uses AI to extract papers important to this topic.
2011
2011
On Different Process Schemes for MOSFETs With a Controllable NiSi-Based Metallic Source/Drain
Jun Luo
,
Dongping Wu
,
+4 authors
Shi-Li Zhang
IEEE Transactions on Electron Devices
2011
Corpus ID: 2213196
This paper focuses on different silicidation schemes toward a controllable NiSi-based metallic source/drain (MSD) process with…
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2009
2009
Advances on 32nm NiPt Salicide process
Yi-Wei Chen
,
Nien-Ting Ho
,
+9 authors
Helen Yang
International Conference on Advanced Thermal…
2009
Corpus ID: 15467819
The two steps RTP program for 32nm NiPt silicide formation process has been evaluated to improve source-drain resistance (Rsd…
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2007
2007
A Novel Low Leakage-Current Ni SALICIDE Process in nMOSFETs on Si(110) Substrate
T. Yamaguchi
,
K. Kashihara
,
+8 authors
M. Kojima
IEEE International Electron Devices Meeting
2007
Corpus ID: 12906979
A novel low leakage-current Ni SALICIDE process in nMOSFETs on Si(110) is proposed. It is found for the first time that the…
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2003
2003
Improvement of poly-silicon hole induced gate oxide failure by silicon rich oxidation
S. Tseng
,
W. Chien
,
B. Cai
Microelectronics and reliability
2003
Corpus ID: 20455006
Highly Cited
2001
Highly Cited
2001
High performance 35 nm gate length CMOS with NO oxynitride gate dielectric and ni SALICIDE
S. Inaba
,
K. Okano
,
+25 authors
H. Ishiuchi
International Electron Devices Meeting. Technical…
2001
Corpus ID: 32942393
35 nm gate length CMOS devices with oxynitride gate dielectric and Ni SALICIDE have been fabricated to study the feasibility of…
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1999
1999
MODELING OF MECHANICAL STRESS IN SILICON ISOLATION TECHNOLOGY AND ITS INFLUENCE ON DEVICE CHARACTERISTICS
H. Rueda
1999
Corpus ID: 110151294
To my family iv ACKNOWLEDGMENTS I would like to express my sincere gratitude to Dr. Mark Law, chairman of my advisory committee…
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1997
1997
A high-performance 0.1 /spl mu/m CMOS with elevated salicide using novel Si-SEG process
H. Wakabayashi
,
T. Yamamoto
,
+4 authors
T. Kunio
International Electron Devices Meeting. IEDM…
1997
Corpus ID: 33900902
High-performance 0.1 /spl mu/m CMOS devices with elevated salicide film for gate electrode and source/drain (S/D) regions and 80…
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1996
1996
A Ti salicide process for 0.10 /spl mu/m gate length CMOS technology
J. Kittl
,
Qi-Zhong Hong
,
D. Prinslow
,
G. Misium
Symposium on VLSI Technology. Digest of Technical…
1996
Corpus ID: 37233576
The fundamental issues for extension of a Ti salicide process to 0.1 /spl mu/m gate length CMOS technologies are presented for…
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1991
1991
A cobalt salicide CMOS process with TiN-strapped polysilicon gates
J. Pfiester
,
T. Mele
,
+4 authors
C. Gunderson
IEEE Electron Device Letters
1991
Corpus ID: 38478876
A submicrometer CMOS technology with MOSFET structures consisting of a TiN-strapped polysilicon gate electrode and self-aligned…
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1989
1989
Limitation of spacer thickness in titanium salicide ULSI CMOS technology
L.J. Sung
,
C. Lu
IEEE Electron Device Letters
1989
Corpus ID: 19512615
The isolation integrity of various gate-spacer thicknesses in 15-20- mu m-wide MOS devices with and without titanium salicide is…
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