Improvement of poly-silicon hole induced gate oxide failure by silicon rich oxidation

@article{Tseng2003ImprovementOP,
  title={Improvement of poly-silicon hole induced gate oxide failure by silicon rich oxidation},
  author={Summer F. C. Tseng and Wei-Ting Kary Chien and Bing-Chu Cai},
  journal={Microelectronics Reliability},
  year={2003},
  volume={43},
  pages={713-724}
}
This paper depicts the improvement of poly-silicon (poly-Si) holes induced failures during gate oxide integrity (GOI) voltage-ramp (V-Ramp) tests by replacing plasma enhanced oxidation with silicon rich oxidation (SRO), which is cap oxide on transfer gate serving as a hard mask to selectively form salicide. The SRO was found to be capable of completely removing salicide block etching induced poly-Si holes. With this SRO film deposited on poly-gate, the higher density silicon in cap oxide fills… CONTINUE READING
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References

Publications referenced by this paper.
Showing 1-10 of 11 references

A study on the effectiveness of different cap oxides for preventing fluorine out-diffusion from FSG

  • PF Chou, YL Cheng
  • IEEE
  • 2001
Highly Influential
10 Excerpts

A new ultra low voltage silicon-rich-oxide (SRO) NAND cell

  • Lin C-J, Hsu CC-H, Chen H-H, G Hong
  • Jpn J Appl Phys 1997;36:1030–4
  • 1997
Highly Influential
10 Excerpts

Plasma charging damage during contact hole etch in high-density plasma etcher

  • BY Tsui
  • Microelectron Reliab
  • 2000

Plasma damage in thin gate MOS dielectrics and its effect on device characteristics and reliability

  • T Brozek
  • Microelectron Reliab 2000;40:625
  • 2000

Reliability of ultra-thin gate oxides for ULSI devices

  • CY Chang
  • Microelectron Reliab
  • 1999

A new experimental technique to evaluate the plasma-induced damage at wafer level testing

  • L Pantisano
  • Microelectron Reliab
  • 1998
1 Excerpt

Damage in thin SiO2–Si structures induced by RIE-mode nitrogen and oxygen plasma

  • A Paskaleva
  • Solid State Electron
  • 1998

Novel ultra-clean self aligned silicide (salicide) technology using double titanium deposited silicide (DTD) process for 0.1 lm gate electrode

  • H Kotaki, M Nakano, K Kataka, S. Kokimoto
  • Jpn J Appl Phys 1998;37:1174–8
  • 1998
1 Excerpt

Plasma induced damage on sub-0.5 lm MOSFETs using a CMOS driver as input protection

  • C Gill, J Porter, P. McEntarfer
  • In: International Symposium on Plasma Process…
  • 1998
1 Excerpt

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