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Polycide
Polycide is a silicide formed over polysilicon. Widely used in DRAMs. In a polycide MOSFET transistor process, the silicide is formed only over the…
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3 relations
Salicide
Transistor
Broader (1)
Semiconductor device fabrication
Papers overview
Semantic Scholar uses AI to extract papers important to this topic.
2005
2005
Lifetime study for a poly fuse in a 0.35 /spl mu/m polycide CMOS process
J. Fellner
,
P. Boesmueller
,
H. Reiter
IEEE International Reliability Physics Symposium…
2005
Corpus ID: 31905416
Poly fuses are used as the base element for one time programmable cells in a standard CMOS process. Using a defined programming…
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2002
2002
The abnormality in gate oxide failure induced by stress-enhanced diffusion of polycrystalline silicon
Yongseok Ahn
,
Sang-Hyeon Lee
,
G. Koh
,
Taeyoung Chung
,
Kinam Kim
Microelectronics and reliability
2002
Corpus ID: 8742865
1997
1997
Direct simulation Monte Carlo of inductively coupled plasma and comparison with experiments
J. Johannes
,
T. Bartel
,
G. Hebner
,
J. Woodworth
,
D. J. Economou
1997
Corpus ID: 15338512
ABSTRACT Direct simulation Monte Carlo was used to study ion and neutral transport and reaction in a low-gas-pressure highplasma…
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1997
1997
A New Tungsten Gate Metal Oxide Semiconductor Capacitor Using a Chemical Vapor Deposition Process
W. Yeh
,
Y. Shiau
,
Mao-chieh Chen
1997
Corpus ID: 58944850
A new process for tungsten gate metal oxide semiconductor (MOS) capacitors has been developed using chemical vapor deposition…
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1997
1997
0.25/spl mu/m W-polycide Dual Gate And Buried Metal On Diffusion Layer (BMD) Technology For DRAM-embedded Logic Devices
Tsukamoto
,
Kuroda
,
Okamoto
Symposium on VLSI Technology
1997
Corpus ID: 43187420
A 0.25pm logic process technology, which is suitable for high-speed, low-voltage operation, logic and DRAM integration in one…
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1992
1992
Dual (n+/p+) Polycide Interconnect Technology using poly-Si/WSiZ/poly-Si Structure and Post B+ Implantation
T. Fujii
,
S. Hashimoto
,
Y. Naito
,
Y. Hirofuji
1992
Corpus ID: 110630504
Formation of low resistance p+ contact was the most difficult problem for Dual(n+/p+) Polycide Interconnect by which both n…
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1991
1991
Technology limitations for N/sup +//P/sup +/ polycide gate CMOS due to lateral dopant diffusion in silicide/polysilicon layers
C. Chu
,
G. Chin
,
K. Saraswat
,
S.S. Wong
,
R. Dutton
IEEE Electron Device Letters
1991
Corpus ID: 37743995
The device degradation of dual-polycide-gate N/sup +//P/sup +/ CMOS polycide transistors due to the lateral diffusion of dopants…
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1991
1991
Direct evidence of gate oxide thickness increase in tungsten polycide processes
S. Hsu
,
L.M. Liu
,
M. Lin
,
C. Chang
IEEE Electron Device Letters
1991
Corpus ID: 29460020
The increase of the effective gate oxide thickness for W-polycide processes is studied. The samples with as-deposited and…
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1989
1989
Avoiding Lateral Diffusion of Dopants in n+/p+ Polycide Gates
D. Amm
,
D. Levy
,
+4 authors
G. Goltz
European Solid-State Device Research Conference
1989
Corpus ID: 36421257
The lateral diffusion of dopants in a TiSi2 salicide process was studied for various BPSG reflow RTP anneals. Lateral diffusion…
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1983
1983
Electromigration Failure in Thin Film Silicides and Polysilicon/Silicide (Polycide) Structures
J. Lloyd
,
M. Sullivan
,
G. Hopper
,
J. Coffin
,
E. Severn
,
J. Jozwiak
IEEE International Reliability Physics Symposium
1983
Corpus ID: 43707553
Thin film conductor stripes (150 nm thick), of silicides of tantalum and tungsten deposited on to thermal oxide as well as…
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