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Polycide

Polycide is a silicide formed over polysilicon. Widely used in DRAMs. In a polycide MOSFET transistor process, the silicide is formed only over the… 
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SalicideTransistor

Broader (1)

Semiconductor device fabrication

Papers overview

Semantic Scholar uses AI to extract papers important to this topic.
2008
2008
CAPTCHA-based Code Voting
: Code voting provides an appropriate technology to address the secure platform problem of remote Internet voting, but it is not… 
2006
2006
Fabricating Nanoscale Features Using the 2-Step NERIME TSI Nanolithography Process
The 2-step negative resist image by dry etching (2-step NERIME) focused ion beam (FIB) top surface imaging (TSI) process is a… 
2005
2005
Lifetime study for a poly fuse in a 0.35 /spl mu/m polycide CMOS process
Poly fuses are used as the base element for one time programmable cells in a standard CMOS process. Using a defined programming… 
2000
2000
Embedded DRAM Technologies : Comparisons and Design Tradeoffs
The use of embedded DRAM technology has become widespread, especially in higher-end system designs, because of its superior… 
1997
1997
Low-resistivity noble integrated clustered electrode (NICE) WSi/sub x/ polycide and its application to a deep sub-quarter micron CMOS
This paper is aimed at suggesting a new technique satisfying the requirement of future devices using a clustered platform, named… 
1994
1994
Dual (n+/p+) Polycide Gate Technology using Si-rich WSix to Exterminate Lateral Dopant Diffusion
We have developed a new technology to solve the device degradation of the dual-polycide-gate N+/P+ CMOS due to the lateral dopant… 
1994
1994
An Inexpensive Diffusion Barrier Technology for Polycide Gate Electrodes with an SiN Layer Formed with ECR Nitrogen Plasma
A.simple diffusjon barrier technology for polycide gate electrodes is proposed. An extremely thin silicon nitride luy"t is.formed… 
1992
1992
Dual (n+/p+) Polycide Interconnect Technology using poly-Si/WSiZ/poly-Si Structure and Post B+ Implantation
Formation of low resistance p+ contact was the most difficult problem for Dual(n+/p+) Polycide Interconnect by which both n… 
1990
1990
The effect of silicon gate microstructure and gate oxide process on threshold voltage instabilities in BF2 implanted P+ gate p-channel MOSFETs
A study of the effects of P+ poly gate microstructure and gate oxide cycle on boron penetration from gate electrode through thin… 
1981
1981
A 34 /spl mu/m/SUP 2/ DRAM cell fabricated with a 1 /spl mu/m single-level polycide FET technology
Dynamic RAM test arrays have been fabricated using a single-level polycide FET technology and a cell layout in which the top… 
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