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Polycide

Polycide is a silicide formed over polysilicon. Widely used in DRAMs. In a polycide MOSFET transistor process, the silicide is formed only over the… 
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3 relations
SalicideTransistor

Broader (1)

Semiconductor device fabrication

Papers overview

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2005
2005
Lifetime study for a poly fuse in a 0.35 /spl mu/m polycide CMOS process
Poly fuses are used as the base element for one time programmable cells in a standard CMOS process. Using a defined programming… 
1999
1999
The formation of Ti-polycide gate structure with high thermal stability using chemical-mechanical polishing (CMP) planarization technology
A planarized Ti-polycide gate structure with high thermal stability has been developed using a chemical-mechanical polishing (CMP… 
1997
1997
Direct simulation Monte Carlo of inductively coupled plasma and comparison with experiments
ABSTRACT Direct simulation Monte Carlo was used to study ion and neutral transport and reaction in a low-gas-pressure highplasma… 
1997
1997
A New Tungsten Gate Metal Oxide Semiconductor Capacitor Using a Chemical Vapor Deposition Process
A new process for tungsten gate metal oxide semiconductor (MOS) capacitors has been developed using chemical vapor deposition… 
1997
1997
0.25/spl mu/m W-polycide Dual Gate And Buried Metal On Diffusion Layer (BMD) Technology For DRAM-embedded Logic Devices
A 0.25pm logic process technology, which is suitable for high-speed, low-voltage operation, logic and DRAM integration in one… 
1993
1993
Decrease of gate oxide dielectric constant in tungsten polycide gate processes
The gate oxide thickness for tungsten (W) polycide gate processes is studied, with tungsten silicide (WSi/sub x/) deposited… 
1992
1992
Dual (n+/p+) Polycide Interconnect Technology using poly-Si/WSiZ/poly-Si Structure and Post B+ Implantation
Formation of low resistance p+ contact was the most difficult problem for Dual(n+/p+) Polycide Interconnect by which both n… 
1991
1991
Direct evidence of gate oxide thickness increase in tungsten polycide processes
The increase of the effective gate oxide thickness for W-polycide processes is studied. The samples with as-deposited and… 
1991
1991
Technology limitations for N/sup +//P/sup +/ polycide gate CMOS due to lateral dopant diffusion in silicide/polysilicon layers
The device degradation of dual-polycide-gate N/sup +//P/sup +/ CMOS polycide transistors due to the lateral diffusion of dopants… 
1989
1989
Avoiding Lateral Diffusion of Dopants in n+/p+ Polycide Gates
The lateral diffusion of dopants in a TiSi2 salicide process was studied for various BPSG reflow RTP anneals. Lateral diffusion… 
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