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Redistribution layer

A redistribution layer (RDL) is an extra metal layer on a chip that makes the IO pads of an integrated circuit available in other locations. When an… 
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Related topics

Related topics

6 relations
Input/outputIntegrated circuitList of integrated circuit packaging typesThree-dimensional integrated circuit

Broader (1)

Semiconductor device fabrication

Papers overview

Semantic Scholar uses AI to extract papers important to this topic.
2017
2017
A routing framework for technology migration with bump encroachment
2014
2014
A Novel Micromachined AlGaN/GaN Power HEMT With Air-Bridged Matrix Heat Redistribution Layer Design
This letter develops a thermally stable micromachined AlGaN/GaN high electron mobility transistor (HEMT) on an Si substrate with… 
2013
2013
A 77 GHz CMOS power amplifier module using multi-layered redistribution layer technology
This paper presents a new millimeter-wave module concept, which is an integration of CMOS monolithic microwave integrated… 
2011
2011
Modelling of through silicon via and devices electromagnetic coupling
2011
2011
Design and optimization of redistribution layer (RDL) on TSV interposer for high frequency applications
The fabrication of redistribution layer (RDL) for TSV 3D integration and its optimization are presented in this paper. BCB is… 
2010
2010
Double side redistribution layer process on embedded wafer level package for package on package (PoP) applications
In this paper, an embedded wafer level package with Cu through mold via (TMV) interconnects was developed for package on package… 
2009
2009
Chip-package codesign with redistribution layer
The use of redistribution layers to connect I/O circuit to the I/O pad is introduced and the electrical performance of a… 
2006
2006
Factorial Analysis of Chip-on-Metal WLCSP Technology with Fan-Out Capability
In this study, a wafer level chip scaled packaging (WLCSP) having the capability of redistributing the electrical circuit is… 
2006
2006
Via-First Inter-Wafer Vertical Interconnects utilizing Wafer-Bonding of Damascene-Patterned Metal/Adhesive Redistribution Layers
Three-dimensional (3D) integration with through-die vias offer improved electrical performance compared to edgeconnected wire… 
2005
2005
Optimal chip-package codesign for high-performance DSP
In high-performance DSP systems, the memory bandwidth can be improved using high-density interconnect technology and appropriate… 
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