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Opcode
Known as:
Instruction opcode
, Opcodes
, Operation code
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In computing, an opcode (abbreviated from operation code, also known as instruction syllable or opstrings.) is the portion of a machine language…
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Related topics
Related topics
49 relations
ARM architecture
Advanced Vector Extensions
Apollo Guidance Computer
Arithmetic logic unit
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Papers overview
Semantic Scholar uses AI to extract papers important to this topic.
2006
2006
Known/Chosen Key Attacks against Software Instruction Set Randomization
Y. Weiss
,
E. G. Barrantes
Asia-Pacific Computer Systems Architecture…
2006
Corpus ID: 14907336
Instruction set randomization (ISR) has been proposed as a form of defense against binary code injection into an executing…
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2006
2006
A VLIW Processor With Hardware Functions: Increasing Performance While Reducing Power
A. Jones
,
R. Hoare
,
D. Kusic
,
J. Stander
,
Gayatri Mehta
,
Joshua Fazekas
IEEE Transactions on Circuits and Systems - II…
2006
Corpus ID: 16292340
This brief presents a heterogeneous multicore embedded processor architecture designed to exceed performance of traditional…
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2006
2006
Rapid VLIW Processor Customization for Signal Processing Applications Using Combinational Hardware Functions
R. Hoare
,
A. Jones
,
+4 authors
M. McCloud
EURASIP Journal on Advances in Signal Processing
2006
Corpus ID: 16497566
This paper presents an architecture that combines VLIW (very long instruction word) processing with the capability to introduce…
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Highly Cited
2001
Highly Cited
2001
A code decompression architecture for VLIW processors
Yuan Xie
,
W. Wolf
,
H. Lekatsas
Proceedings. 34th ACM/IEEE International…
2001
Corpus ID: 7446827
In embedded system design, memory has been one of the most restricted resources. Reducing program size has been an important goal…
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Highly Cited
1999
Highly Cited
1999
Instruction Scheduling for TriMedia
J. Hoogerbrugge
,
L. Augusteijn
J. Instr. Level Parallelism
1999
Corpus ID: 12207169
Instruction scheduling is a crucial phase in a compiler for very long instruction word (VLIW) processors. This paper describes…
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Highly Cited
1994
Highly Cited
1994
Design of transport triggered architectures
H. Corporaal
Proceedings of 4th Great Lakes Symposium on VLSI
1994
Corpus ID: 45520512
Transport triggered architectures (TTAs) form a superclass of traditional very large instruction word (VLIW) architectures, in…
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1990
1990
Benchmarking Advanced Architecture Computers
P. Messina
,
C. Baillie
,
+8 authors
D. Walker
Concurrency Practice and Experience
1990
Corpus ID: 29863655
Recently, a number of advanced architecture machines have become commercially available. These new machines promise better cost…
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1986
1986
A new synthesis for the MIMOLA software system
P. Marwedel
Design Automation Conference
1986
Corpus ID: 46001959
The MIMOLA software system is a system for the design of digital processors. The system includes subsystems for retargetable…
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1982
1982
Empirical analysis of the mesa instruction set
Richard E. Sweet
,
James G. Sandman
ASPLOS I
1982
Corpus ID: 1353842
This paper describes recent work to refine the instruction set of the Mesa processor. Mesa [8] is a high level systems…
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1971
1971
Conditional Interpretation of Operation Codes
C. C. Foster
,
R. Gonter
IEEE transactions on computers
1971
Corpus ID: 33179555
A method, called conditional interpretation, is proposed which will allow small computers to have as large a set of instructions…
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