Skip to search formSkip to main contentSkip to account menu

Opcode

Known as: Instruction opcode, Opcodes, Operation code 
In computing, an opcode (abbreviated from operation code, also known as instruction syllable or opstrings.) is the portion of a machine language… 
Wikipedia (opens in a new tab)

Related topics

Related topics

49 relations
ARM architectureAdvanced Vector ExtensionsApollo Guidance ComputerArithmetic logic unit

Papers overview

Semantic Scholar uses AI to extract papers important to this topic.
2007
2007
An Integrated Memory Array Processor for Embedded Image Recognition Systems
Embedded processors for video image recognition in most cases not only need to address the conventional cost (die size and power… 
Review
2005
Review
2005
SNBENCH: a development and run-time platform for rapid deployment of sensor network applications
We envision the emergence of general-purpose, well-provisioned sensor networks - which we call "Sensoria" - that are embedded in… 
2003
2003
A statistical adaptive block-matching motion estimation
We address the problem of motion estimation (ME) in digital video sequences and propose a new fast, adaptive, and efficient block… 
2003
2003
Care bit density and test cube clusters: multi-level compression opportunities
  • Bernd Könemann
  • Proceedings 21st International Conference on…
  • 2003
  • Corpus ID: 17000628
Most of the recently discussed and commercially introduced test stimulus data compression techniques are based on low care bit… 
2002
2002
The Equator MAP-CA™ DSP: an end-to-end broadband signal processor™ VLIW
Today's multimedia services, both at the server/headend and the client/consumer end, require high computational performance to… 
2001
2001
Real-time implementation and optimization of ITU-T's G.729 speech codec running at 8 kbits/sec using CS-ACELP on TM-1000 VLIW DSP CPU
During the history of digital audio compression there have been many different attempts at reducing the bit rate without reducing… 
2001
2001
The first MAJC microprocessor: a dual CPU system-on-a-chip
The first implementation of MAJC architecture achieves high performance by using very long instruction word (VLIW), single… 
Highly Cited
1999
Highly Cited
1999
Instruction Scheduling for TriMedia
Instruction scheduling is a crucial phase in a compiler for very long instruction word (VLIW) processors. This paper describes… 
1999
1999
Active Page Architectures for Media Processing
In this paper, we compare the performance of various media applications on vector and VLIW Active Page OCS98] memory… 
1998
1998
Edgebreaker: Compressing the incidence graph of triangle meshes
Edgebreaker is a simple scheme for compressing the triangle/vertex incidence graphs (sometimes called topology) of… 
By clicking accept or continuing to use the site, you agree to the terms outlined in our Privacy Policy (opens in a new tab), Terms of Service (opens in a new tab), and Dataset License (opens in a new tab)