• Publications
  • Influence
Efficient Execution of Process Networks
TLDR
This work presents techniques for the efficient ex- ecution of KPNs, taking into account both execution time and memory usage. Expand
Homogeneous multiprocessing and the future of silicon design paradigms
TLDR
The paper derives a relation between on-chip memory real estate and compute logic, suggesting that homogeneous multiprocessors are an unavoidable consequence of the technology curve and presents the implementation of a programming paradigm that focuses on reuse of tested and approved functions at the software level. Expand
Transport-Triggering versus Operation-Triggering
TLDR
Experiments are reported that quantify the advantages of transport-triggered architectures with respect to traditional operation-trIGgered architectures. Expand
Dynamic branch prediction for a VLIW processor
  • J. Hoogerbrugge
  • Computer Science
  • Proceedings International Conference on Parallel…
  • 15 October 2000
TLDR
The design of a dynamic branch predictor for a VLIW processor is described and it is proposed to have both predicted and delayed branches in the ISA and let the compiler select which type to apply. Expand
Code generation for transport triggered architectures
TLDR
Transport triggered architectures form a class of architectures which are programmed by specifying data transports between function units, which makes these data transports visible at the architectural level and enables several extra code scheduling optimizations. Expand
Parallel H.264 Decoding on an Embedded Multicore Processor
TLDR
This work presents an implementation of the 3D-Wave parallelization strategy on a multicore architecture composed of NXP TriMedia TM3270 embedded processors and shows that the parallel H.264 implementation scales very well, achieving a speedup of more than 54 on a 64-core processor. Expand
A code compression system based on pipelined interpreters
TLDR
Experiments are described that demonstrate the compression quality of the system and the execution speed of the pipelined interpreter; these were found to be about five times more compact than native TriMedia code and a slowdown of about eight times, respectively. Expand
Register file port requirements of transport triggered architectures
TLDR
This paper shows that the new class of transport triggered architectures requires fewer ports on the shared register file than traditional operation triggered architectures by programming data-transports instead of operations. Expand
ConCISe: a compiler-driven CPLD-based instruction set accelerator
TLDR
A smart compilation chain in which the compiler is no longer limited by a pre-defined instruction set, but can generate application-specific custom instructions and synthesise them in Field-Programmable Logic to reduce the reconfiguration overhead and optimise the utilisation of resources is proposed. Expand
A Code Compression System Based on Pipelined Interpreters
TLDR
Experiments are described that demonstrate the compression quality of the system and the execution speed of the pipelined interpreter; these were found to be about five times more compact than native TriMedia code and a slowdown of about eight times, respectively. Expand
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