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Advanced Vector Extensions
Known as:
YMM9 register
, YMM8 register
, YMM7 register
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Advanced Vector Extensions (AVX) are extensions to the x86 instruction set architecture for microprocessors from Intel and AMD proposed by Intel in…
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Related topics
Related topics
50 relations
256-bit
Addressing mode
Broadwell (microarchitecture)
Bulldozer (microarchitecture)
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Papers overview
Semantic Scholar uses AI to extract papers important to this topic.
2017
2017
Exploiting Asymmetric SIMD Register Configurations in ARM-to-x86 Dynamic Binary Translation
Yu-Ping Liu
,
Ding-Yong Hong
,
Jan-Jan Wu
,
Sheng-Yu Fu
,
W. Hsu
International Conference on Parallel…
2017
Corpus ID: 20913735
Processor manufacturers have adopted SIMD for decades because of its superior performance and power efficiency. The…
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Review
2016
Review
2016
Vectorization on Intel Xeon Phi: A Survey Approach
N. Tiwari
,
P. Vidap
2016
Corpus ID: 212487620
In computer science, vectorization is the process of converting an algorithm from a scalar implementation to a vector process. It…
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2015
2015
An investigation of compiler vectorization on current and next-generation Intel processors using benchmarks and Sandia?s Sierra applications.
M. Rajan
,
D. Doerfler
,
M. Tupek
,
S. Hammond
2015
Corpus ID: 8067961
Sandia and Los Alamos National Laboratories are acquiring Trinity, a Cray XC40, with half of the nodes having Haswell processors…
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2014
2014
Vectorization of an augmented Riemann solver for the shallow water equations
M. Bader
,
Alexander Breuer
,
W. Holzl
,
Sebastian Rettenberger
International Symposium on High Performance…
2014
Corpus ID: 8052655
We discuss the vectorization of two different Riemann solvers for the shallow water equations. For a wave propagation method that…
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2013
2013
Split-Path Fused Floating Point Multiply Accumulate (FPMAC)
S. Srinivasan
,
Ketan Bhudiya
,
+5 authors
V. Erraguntla
IEEE Symposium on Computer Arithmetic
2013
Corpus ID: 13992494
Floating point multiply-accumulate (FPMAC) unitis the backbone of modern processors and is a key circuit determining the…
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2012
2012
Performance evaluation of Intel Xeon E5-2600 family cluster using scientific and engineering benchmarks
P. Gepner
,
D. L. Fraser
,
V. Gamayunov
2nd IEEE International Conference on Parallel…
2012
Corpus ID: 15771061
In this paper, we present an performance evaluation of a 256-core cluster based on the Intel Xeon Processor E5-2680. This is the…
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2012
2012
Implementing BLAKE with AVX, AVX2, and XOP
Samuel Neves
,
Jean-Philippe Aumasson
IACR Cryptology ePrint Archive
2012
Corpus ID: 8225311
In 2013 Intel will release the AVX2 instructions, which introduce 256-bit singleinstruction multiple-data (SIMD) integer…
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2010
2010
SAC : An Efficient Retargetable Source-to-Source Compiler for Multimedia Instruction Sets
2010
Corpus ID: 16353897
Multimedia instruction sets allow developments of time and power efficient applications. As a consequence they are widely used in…
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2009
2009
High-performance synthetic aperture radar image formation on commodity multicore architectures
Daniel S. McFarlin
,
F. Franchetti
,
Markus Püschel
,
José M. F. Moura
Defense + Commercial Sensing
2009
Corpus ID: 12403234
Synthetic Aperture Radar (SAR) image processing platforms have to process increasingly large datasets under and hard real-time…
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Highly Cited
2007
Highly Cited
2007
Systematic Continuous Adjoint Approach to Viscous Aerodynamic Design on Unstructured Grids
C. Castro
,
C. Lozano
,
F. Palacios
,
E. Zuazua
2007
Corpus ID: 56573300
DOI: 10.2514/1.24859 A continuous adjoint approach to aerodynamic design for viscous compressible flow on unstructured grids is…
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