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Addressing mode
Known as:
Indirect addressing
, Load Effective Address
, Indirect address
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Addressing modes are an aspect of the instruction set architecture in most central processing unit (CPU) designs. The various addressing modes that…
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Related topics
Related topics
48 relations
ARM architecture
Accumulator (computing)
Advanced Vector Extensions
Adventure
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Papers overview
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2014
2014
Modeling and analyzing performance for highly optimized propagation steps of the lattice Boltzmann method on sparse lattices
M. Wittmann
,
T. Zeiser
,
G. Hager
,
G. Wellein
arXiv.org
2014
Corpus ID: 8094198
Computational fluid dynamics (CFD) requires a vast amount of compute cycles on contemporary large-scale parallel computers. Hence…
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2013
2013
INTRODUCTION TO STORING GRAPHS BY NL-ADDRESSING
K. Ivanova
,
K. Vanhoof
,
K. Markov
,
V. Velychko
2013
Corpus ID: 123172982
This paper introduces an approach to storing graphs based on the Natural Language Addressing in multidimensional numbered…
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2010
2010
Ganey Knowledge Summary : Patient Satisfaction with Emotional and Spiritual Care
2010
Corpus ID: 40033149
BACKGROUND: Since 1985, Press Ganey has measured patient satisfaction with the experience of care using a holistic perspective…
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2004
2004
Design and performance of turbo Gallager codes
G. Colavolpe
IEEE Transactions on Communications
2004
Corpus ID: 16468300
The most powerful channel-coding schemes, namely, those based on turbo codes and low-density parity-check (LDPC) Gallager codes…
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2001
2001
Fundamentals of Embedded Software: Where C and Assembly Meet with Cdrom
D. Lewis
2001
Corpus ID: 59642517
From the Publisher: Fundamentals of Embedded Software: Where C and Assembly Meet is a refreshing alternative to the traditional…
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1991
1991
Lilac: a two-view document editor
Kenneth P. Brooks
Computer
1991
Corpus ID: 2239112
A description is given of Lilac, an experimental document preparation system designed to provide the best of both the WYSIWYG…
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1990
1990
Systolic array implementations of neural nets on the MasPar MP-1 massively parallel processor
G. Chinn
,
K. Grajski
,
C. Chen
,
C. Kuszmaul
,
S. Tomboulian
IJCNN International Joint Conference on Neural…
1990
Corpus ID: 29483714
It is shown that systolic array design techniques commonly used by VLSI designers can be used to realize neural nets on parallel…
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1989
1989
Capability based, tightly coupled multiprocessor hardware to support a persistent global virtual memory
R. Pose
[] Proceedings of the Twenty-Second Annual Hawaii…
1989
Corpus ID: 61499585
A capability-based tightly coupled multiprocessor has been designed and constructed. The system supports a persistent global…
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1989
1989
A frontal technique for vector computers
L. Brusa
,
F. Riccio
1989
Corpus ID: 62189591
At the kernel of most scientific computations lies the solution of linear equations which, in finite element codes, is often…
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1979
1979
A 32-bit processor design
Stephen C. Johnson
1979
Corpus ID: 15618533
This paper describes a user-level instruction set for a 32-bit processor. The machine is simple, compact, and well suited to the…
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