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Addressing mode
Known as:
Indirect addressing
, Load Effective Address
, Indirect address
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Addressing modes are an aspect of the instruction set architecture in most central processing unit (CPU) designs. The various addressing modes that…
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Related topics
Related topics
48 relations
ARM architecture
Accumulator (computing)
Advanced Vector Extensions
Adventure
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Papers overview
Semantic Scholar uses AI to extract papers important to this topic.
2008
2008
A scalable configurable architecture for the massively parallel GCA model
Johannes Jendrsczok
,
Patrick Ediger
,
R. Hoffmann
IEEE International Symposium on Parallel and…
2008
Corpus ID: 16108792
The global cellular automata model (GCA) is a massively parallel computation model which extends the classical cellular automata…
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2006
2006
Leaky modes of slab waveguides-asymptotic solutions
Jianxin Zhu
,
Y. Lu
Journal of Lightwave Technology
2006
Corpus ID: 6045267
Approximate analytic solutions of the leaky modes in two-dimensional slab waveguides are derived through an asymptotic analysis…
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2004
2004
Design of high-performance system-on-chips using communication architecture tuners
K. Lahiri
,
A. Raghunathan
,
G. Lakshminarayana
,
S. Dey
IEEE Transactions on Computer-Aided Design of…
2004
Corpus ID: 3144627
In this paper, we present a methodology for the design of high-performance system-on-chip communication architectures. The…
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2003
2003
Multi-rate digital control with interlacing and its application to hard disk drive servo
Shang-Chen Wu
,
M. Tomizuka
Proceedings of the American Control Conference…
2003
Corpus ID: 61206501
This paper presents a design method for a multi-rate digital controller with interlacing and its application to hard disk drives…
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2001
2001
Fundamentals of Embedded Software: Where C and Assembly Meet with Cdrom
D. Lewis
2001
Corpus ID: 59642517
From the Publisher: Fundamentals of Embedded Software: Where C and Assembly Meet is a refreshing alternative to the traditional…
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1996
1996
Instruction set design and optimizations for address computation in DSP architectures
G. Araújo
,
A. Sudarsanam
,
S. Malik
Proceedings of 9th International Symposium on…
1996
Corpus ID: 7263300
In this paper we investigate the problem of code generation for address computation for DSP processors. This work is divided into…
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1996
1996
A 3.84 gips integrated memory array processor
Y. Fujita
,
N. Yamashita
,
Tohru Kimura
,
Kazuyuki Nakamura
,
S. Okazaki
Systems and Computers in Japan
1996
Corpus ID: 6174086
An integrated memory array processor (IMAP) ULSI with 64 processing elements and a 2 Mb SRAM has been developed to build a…
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1991
1991
Frontal algorithms for equation-based chemical process flowsheeting on vector and parallel computers
S. Zitney
1991
Corpus ID: 56838256
Highly Cited
1991
Highly Cited
1991
A comparative study of automatic vectorizing compilers
D. Levine
,
D. Callahan
,
J. Dongarra
Parallel Computing
1991
Corpus ID: 6144088
1990
1990
Systolic array implementations of neural nets on the MasPar MP-1 massively parallel processor
G. Chinn
,
K. Grajski
,
C. Chen
,
C. Kuszmaul
,
S. Tomboulian
IJCNN International Joint Conference on Neural…
1990
Corpus ID: 29483714
It is shown that systolic array design techniques commonly used by VLSI designers can be used to realize neural nets on parallel…
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