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Addressing mode
Known as:
Indirect addressing
, Load Effective Address
, Indirect address
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Addressing modes are an aspect of the instruction set architecture in most central processing unit (CPU) designs. The various addressing modes that…
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Related topics
Related topics
48 relations
ARM architecture
Accumulator (computing)
Advanced Vector Extensions
Adventure
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Papers overview
Semantic Scholar uses AI to extract papers important to this topic.
2008
2008
A relational approach to supervision: Addressing ruptures in the alliance.
J. Safran
,
J. Muran
,
Christopher Stevens
,
Michael Rothman
2008
Corpus ID: 157025184
Establishing, sustaining, and repairing ruptures in the therapeutic alliance are among the most important competencies in…
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2007
2007
Forensic computing - a practitioner's guide (2. ed.)
A. J. Sammes
,
B. Jenkinson
2007
Corpus ID: 59984651
With the advancement of the digital era, the digital crime (aka cyber crime) increasing day-by-day. This lead to the era of…
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2004
2004
Design of high-performance system-on-chips using communication architecture tuners
K. Lahiri
,
A. Raghunathan
,
G. Lakshminarayana
,
S. Dey
IEEE Transactions on Computer-Aided Design of…
2004
Corpus ID: 3144627
In this paper, we present a methodology for the design of high-performance system-on-chip communication architectures. The…
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2001
2001
Fundamentals of Embedded Software: Where C and Assembly Meet with Cdrom
D. Lewis
2001
Corpus ID: 59642517
From the Publisher: Fundamentals of Embedded Software: Where C and Assembly Meet is a refreshing alternative to the traditional…
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1997
1997
An extended addressing mode for low power
Atul Kalambur
,
M. J. Irwin
Proceedings / International Symposium on Low…
1997
Corpus ID: 14827713
This paper demonstrates the feasibility of a register-memory addressing mode in microprocessors targeted for low power…
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1996
1996
A 3.84 gips integrated memory array processor
Y. Fujita
,
N. Yamashita
,
Tohru Kimura
,
Kazuyuki Nakamura
,
S. Okazaki
Systems and Computers in Japan
1996
Corpus ID: 6174086
An integrated memory array processor (IMAP) ULSI with 64 processing elements and a 2 Mb SRAM has been developed to build a…
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Highly Cited
1994
Highly Cited
1994
An integrated approach to retargetable code generation
T. C. Wilson
,
G. Grewal
,
B. Halley
,
D. Banerji
Proceedings of 7th International Symposium on…
1994
Corpus ID: 14384424
Special-purpose instruction set processors (ISPs) challenge compilers because of instruction level parallelism, small numbers of…
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1991
1991
Frontal algorithms for equation-based chemical process flowsheeting on vector and parallel computers
S. Zitney
1991
Corpus ID: 56838256
Highly Cited
1991
Highly Cited
1991
A comparative study of automatic vectorizing compilers
D. Levine
,
D. Callahan
,
J. Dongarra
Parallel Computing
1991
Corpus ID: 6144088
1967
1967
Considerations in block-oriented systems design
Donald H. Gibson
AFIPS '67 (Spring)
1967
Corpus ID: 15316786
The feasibility of transmitting blocks of words between memory and CPU is the subject of this study. The question is pertinent to…
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