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Addressing mode
Known as:
Indirect addressing
, Load Effective Address
, Indirect address
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Addressing modes are an aspect of the instruction set architecture in most central processing unit (CPU) designs. The various addressing modes that…
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Related topics
Related topics
48 relations
ARM architecture
Accumulator (computing)
Advanced Vector Extensions
Adventure
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Papers overview
Semantic Scholar uses AI to extract papers important to this topic.
2010
2010
Ganey Knowledge Summary : Patient Satisfaction with Emotional and Spiritual Care
2010
Corpus ID: 40033149
BACKGROUND: Since 1985, Press Ganey has measured patient satisfaction with the experience of care using a holistic perspective…
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2007
2007
Forensic computing - a practitioner's guide (2. ed.)
A. J. Sammes
,
B. Jenkinson
2007
Corpus ID: 59984651
With the advancement of the digital era, the digital crime (aka cyber crime) increasing day-by-day. This lead to the era of…
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2004
2004
Design and performance of turbo Gallager codes
G. Colavolpe
IEEE Transactions on Communications
2004
Corpus ID: 16468300
The most powerful channel-coding schemes, namely, those based on turbo codes and low-density parity-check (LDPC) Gallager codes…
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2001
2001
Fundamentals of Embedded Software: Where C and Assembly Meet with Cdrom
D. Lewis
2001
Corpus ID: 59642517
From the Publisher: Fundamentals of Embedded Software: Where C and Assembly Meet is a refreshing alternative to the traditional…
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1999
1999
A segmented gray code for low-power microcontroller address buses
R. Hakenes
,
Y. Manoli
Proceedings 25th EUROMICRO Conference…
1999
Corpus ID: 11732505
The paper presents a novel approach to using the switching activity enhancements of a gray code on high capacitive…
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1998
1998
Load execution latency reduction
Bryan Black
,
Brian Mueller
,
Stephanie Postal
,
R. Rakvic
,
N. Utamaphethai
,
John Paul Shen
International Conference on Supercomputing
1998
Corpus ID: 2229973
Load execution latency is dependent on memory access latency, pipeline depth, and data dependencies. Through load effective…
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1994
1994
Memory Aspects and Performance of Iterative Solvers
C. Pommerell
,
W. Fichtner
SIAM Journal on Scientific Computing
1994
Corpus ID: 8109804
In many scientific computing problems, the overall execution time is dominated by the time to solve very large linear systems…
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1990
1990
Systolic array implementations of neural nets on the MasPar MP-1 massively parallel processor
G. Chinn
,
K. Grajski
,
C. Chen
,
C. Kuszmaul
,
S. Tomboulian
IJCNN International Joint Conference on Neural…
1990
Corpus ID: 29483714
It is shown that systolic array design techniques commonly used by VLSI designers can be used to realize neural nets on parallel…
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1989
1989
Capability based, tightly coupled multiprocessor hardware to support a persistent global virtual memory
R. Pose
[] Proceedings of the Twenty-Second Annual Hawaii…
1989
Corpus ID: 61499585
A capability-based tightly coupled multiprocessor has been designed and constructed. The system supports a persistent global…
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1960
1960
The Design of a General-Purpose Microprogam-Controlled Computer with Elementary Structure
Thomas W. Kampe
IRE Transactions on Electronic Computers
1960
Corpus ID: 40676242
This paper presents the design of a parallel digital computer utilizing a 20-?sec core memory and a diode storage microprogram…
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