• Publications
  • Influence
Microprocessor architectures - from VLIW to TTA
TLDR
This work introduces a new type of computer architecture, the transport triggered architecture (TTA), designed to alleviate delay problems in existing instruction-level parallel architectures. Expand
Memory-centric accelerator design for Convolutional Neural Networks
TLDR
It is shown that the effects of the memory bottleneck can be reduced by a flexible memory hierarchy that supports the complex data access patterns in CNN workload and ensures that on-chip memory size is minimized, which reduces area and energy usage. Expand
A detailed GPU cache model based on reuse distance theory
TLDR
This work extends reuse distance to GPUs by modelling the GPU's hierarchy of threads, warps, threadblocks, and sets of active threads, including conditional and non-uniform latencies, cache associativity, miss-status holding-registers, and warp divergence. Expand
Multiprocessor Resource Allocation for Throughput-Constrained Synchronous Dataflow Graphs
TLDR
A new resource allocation strategy which works directly on SDFGs is presented, building on an efficient technique to calculate throughput of a bound and scheduled SDFG, and experimental results show that the strategy is effective in terms of run-time and allocated resources. Expand
High performance predictable histogramming on GPUs: exploring and evaluating algorithm trade-offs
TLDR
This paper presents two novel histogramming methods, both achieving a higher performance and predictability than existing methods and guarantees to be fully data independent. Expand
Transport Triggered Architectures : Design and Evaluation
Introducing 'Bones': a parallelizing source-to-source compiler based on algorithmic skeletons
TLDR
A new classification of algorithms is used in a new source-to-source compiler, which is based on the algorithmic skeletons technique, and it is demonstrated that the presented compiler requires little modifications to the original sequential source code, generates readable code for further fine-tuning, and delivers superior performance compared to other tools for a set of 8 image processing kernels. Expand
Design of transport triggered architectures
  • H. Corporaal
  • Computer Science
  • Proceedings of 4th Great Lakes Symposium on VLSI
  • 4 March 1994
TLDR
The paper discusses the concept of transport triggering and its corresponding advantages, and further concentrates on a prototype VLSI implementation in a 1.6 /spl mu/ Sea of Gates technology, called MOVE32INT, which demonstrates the feasibility of transport triggers. Expand
System-scenario-based design of dynamic embedded systems
TLDR
A generic and systematic design-time/run-time methodology for handling the dynamic nature of modern embedded systems, based on the concept of system scenarios, that allows the system to learn on-the-fly during its execution, and to adapt itself to the current input stimuli. Expand
Embedded System Design
since 1998 in which over 60 academic researchers collaborated with industrial colleagues. Through its setup and its results PROGRESS has become a landmark on demand-driven academic research in TheExpand
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