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GgNMOS
Grounded-gate NMOS, commonly known as ggNMOS, is an electrostatic discharge (ESD) protection device used within CMOS integrated circuits (ICs). Such…
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6 relations
CMOS
Parasitic structure
Printed circuit board
Semiconductor package
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Papers overview
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2018
2018
Physics of Current Filamentation in ggNMOS Devices Under ESD Condition Revisited
Milova Paul
,
C. Russ
,
B. Kumar
,
H. Gossner
,
M. Shrivastava
IEEE Transactions on Electron Devices
2018
Corpus ID: 49268631
This paper revisits the physics of current filamentation in grounded-gate NMOS (ggNMOS) devices and presents new physical…
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2015
2015
ESD characterization of diodes and ggMOS in Germanium FinFET technologies
R. Boschke
,
D. Linten
,
+7 authors
G. Groeseneken
Electrical Overstress/Electrostatic Discharge…
2015
Corpus ID: 38224403
Germanium as a high mobility material is a candidate to replace Silicon as channel material for future scaled FinFETs. This work…
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2013
2013
New GGNMOS I/O Cell Array for Improved Electrical Overstress Robustness
Yon-Sup Pang
,
Youngjun Kim
2013
Corpus ID: 54790907
A 0.18-μm 3.3 V grounded-gate NMOS (GGNMOS) I/O cell array for timing controller (TCON) application is proposed for improving…
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2012
2012
ESD protection devices placed inside keep-out zone (KOZ) of through Silicon Via (TSV) in 3D stacked integrated circuits
Shih-Hung Chen
,
S. Thijs
,
D. Linten
,
M. Scholz
,
G. Hellings
,
G. Groeseneken
Electrical Overstress / Electrostatic Discharge…
2012
Corpus ID: 40115007
Through Silicon Via (TSV) has been utilized in vertically stacking IC dice to implement real system-in-chip applications. However…
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2006
2006
ESD Robustness of 40-V CMOS Devices With/Without Drift Implant
W. Chang
,
M. Ker
,
T. Lai
,
Tien-Hao Tang
,
K. Su
IEEE International Integrated Reliability…
2006
Corpus ID: 18228917
The dependences of device structures and layout parameters on ESD robustness in a 40-V CMOS process have been investigated in…
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2005
2005
ESD-RF co-design methodology for the state of the art RF-CMOS blocks
Vesselin K. Vassilev
,
S. Thijs
,
+6 authors
M. Steyaert
Microelectronics and reliability
2005
Corpus ID: 23924331
2003
2003
TLP analysis of 0.125 μm CMOS ESD input protection circuit
M. Chaine
,
James Davis
,
Al Kearney
Electrical Overstress/Electrostatic Discharge…
2003
Corpus ID: 34624487
2003
2003
Investigation of thermal breakdown mechanism in 0. 13 /spl mu/m technology ggNMOS under ESD conditions
L. M. Hillkirk
,
J. Chun
,
Robert W. Dutton
International Conference on Simulation of…
2003
Corpus ID: 13850110
Transient device simulations reproducing conditions similar to Electro-Static Discharge (ESD) conditions have been performed for…
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2002
2002
Emitter injection control in LVTSCR for latch-up free ESD protection
V. Vashchenko
,
A. Concannon
,
M. ter Beek
,
P. Hopper
23rd International Conference on Microelectronics…
2002
Corpus ID: 61527329
A low-voltage triggered silicon controlled rectifier with optimized holding voltage for ESD protection, has been developed and is…
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2001
2001
ESD-Induced Circuit Performance Degradation in RFICs
K. Gonf
,
H. Feng
,
R. Zhan
,
A. Wang
Microelectronics and reliability
2001
Corpus ID: 12119311
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