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Front end of line
Known as:
FEOL
, Front-end-of-line
The front-end-of-line (FEOL) is the first portion of IC fabrication where the individual devices (transistors, capacitors, resistors, etc.) are…
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Related topics
Related topics
12 relations
Back end of line
CMOS
Chemical-mechanical planarization
Integrated circuit
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Broader (1)
Semiconductor device fabrication
Papers overview
Semantic Scholar uses AI to extract papers important to this topic.
2018
2018
Highly Manufacturable Low Power and High Performance 11LPP Platform Technology for Mobile and GPU Applications
H. Kim
,
B.H. Choi
,
+10 authors
J. Yoon
IEEE Symposium on VLSI Technology
2018
Corpus ID: 53092107
11nm bulk FinFET process employing 3rd generation 14nm FEOL and 10nm BEOL process has been successfully demonstrated with updated…
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2018
2018
Factor Analysis of Plasma-Induced Damage in Bulk FinFET Technology
G. Hiblot
,
G. van der Plas
IEEE Electron Device Letters
2018
Corpus ID: 49539770
In this letter, factor analysis is employed to investigate the hidden dependencies and correlations of plasma-induced damage with…
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Review
2017
Review
2017
Prospects for Electronic Photonic Integration
K. Williams
2017
Corpus ID: 85534169
As InP integrated photonic circuits increase in complexity, component density, and circuit performance, electronic circuits need…
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2015
2015
Automatic obfuscated cell layout for trusted split-foundry design
Carlos Tadeo Ortega Otero
,
Jonathan Tse
,
Robert Karmazin
,
Benjamin Hill
,
R. Manohar
IEEE International Symposium on Hardware Oriented…
2015
Corpus ID: 10510955
We present split-cellTK, a tool that automates the obfuscation of split-foundry layout, in which an untrusted foundry fabricates…
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2015
2015
Beyond the Interconnections: Split Manufacturing in RF Designs
Yu Bi
,
Jiann-Shiun Yuan
,
Yier Jin
Electronics
2015
Corpus ID: 11134488
With the globalization of the integrated circuit (IC) design flow of chip fabrication, intellectual property (IP) piracy is…
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2013
2013
Effect of TSV presence on FEOL yield and reliability
T. Kauerauf
,
A. Brańka
,
+5 authors
E. Beyne
IEEE International Reliability Physics Symposium
2013
Corpus ID: 30628546
In this work we evaluate the impact of TSV processing and proximity on transistor performance and reliability by monitoring key…
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2010
2010
Monte Carlo Simulations to Evaluate the Contribution of Si Bulk, Interconnects, and Packaging to Alpha-Soft Error Rates in Advanced Technologies
M. Gedion
,
F. Wrobel
,
F. Saigné
,
peixiong zhao
,
J. Mekki
IEEE Transactions on Nuclear Science
2010
Corpus ID: 43546902
At ground level, alpha particles are a major source of soft errors. They may result from radioactive isotopes found in electronic…
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2009
2009
Via first approach optimisation for Through Silicon Via applications
C. Laviron
,
B. Dunne
,
+7 authors
N. Sillon
Electronic Components and Technology Conference
2009
Corpus ID: 26877714
Through Silicon Via (TSV) is a very attractive solution for 3D stacking. Currently the main technique in industrial TSV processes…
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2009
2009
Polysilicon interconnections (FEOL): Fabrication and characterization
A. Agarwal
,
R. Murthy
,
V. Lee
,
G. Viswanadam
Electronic Packaging Technology Conference
2009
Corpus ID: 24876132
Three dimensional silicon integration technologies are gaining considerable attention as the traditional CMOS scaling becoming…
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2007
2007
Carbon / high-k Trench Capacitor for the 40nm DRAM Generation
G. Aichmayr
,
A. Avellan
,
G. Duesberg
,
F. Kreupl
,
S. Kudelka
,
M. Liebau
IEEE Symposium on VLSI Technology
2007
Corpus ID: 1073993
Carbon is proposed as a new FEOL material with high conductivity and thermal stability for CMOS integration. Here the application…
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