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Back end of line

Known as: BEOL 
The back end of line (BEOL) is the second portion of IC fabrication where the individual devices (transistors, capacitors, resistors, etc.) get… 
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Related topics

Related topics

13 relations
Alpha 21064Chemical vapor depositionChemical-mechanical planarizationCopper interconnect

Broader (1)

Semiconductor device fabrication

Papers overview

Semantic Scholar uses AI to extract papers important to this topic.
2014
2014
Stress analyses of high spatial resolution on TSV and BEoL structures
2012
2012
Interconnect design and analysis for Through Silicon Interposers (TSIs)
The trend of increasing digital system performance by downscaling the device size poses daunting challenges in system design due… 
Review
2007
Review
2007
Design for millimeter-wave applications in silicon technologies
This paper presents the potentialities of advanced BiCMOS and CMOS technologies for millimeter-wave applications. To begin, the… 
2006
2006
Back-End-Of-Line Poly-Sige Disk Resonators
This paper reports the characterization of poly-silicon-germanium disk resonators at frequencies ranging from 35 to 425MHz. The… 
Review
2006
Review
2006
Cu Alloy Metallization for Self-Forming Barrier Process
A novel Cu-Mn alloy has been developed to self-form a diffusion barrier layer at metal/dielectric interface without depositing a… 
Highly Cited
2005
Highly Cited
2005
High performance 65 nm SOI technology with enhanced transistor strain and advanced-low-K BEOL
A high performance 65 nm SOI CMOS technology is presented. Dual stress liner (DSL), embedded SiGe, and stress memorization… 
Highly Cited
2004
Highly Cited
2004
Nonvolatile memory based on solid electrolytes
Programmable metallization cell (PMC) memory utilizes electrochemical control of nanoscale quantities of metal in thin films of… 
2004
2004
A 0.314/spl mu/m/sup 2/ 6T-SRAM cell build with tall triple-gate devices for 45nm applications using 0.75NA 193nm lithography
This paper describes the fabrication process of a fully working 6T-SRAM cell of 0.314/spl mu/m/sup 2/ build with tall triple gate… 
2002
2002
Integration of high-performance, low-leakage and mixed signal features into a 100 nm CMOS technology
Low voltage operation in sub-0.25 /spl mu/m requirements mean that the simultaneous integration of all components on a single… 
Highly Cited
2001
Highly Cited
2001
High performance 35 nm gate length CMOS with NO oxynitride gate dielectric and ni SALICIDE
35 nm gate length CMOS devices with oxynitride gate dielectric and Ni SALICIDE have been fabricated to study the feasibility of… 
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