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Back end of line
Known as:
BEOL
The back end of line (BEOL) is the second portion of IC fabrication where the individual devices (transistors, capacitors, resistors, etc.) get…
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Related topics
Related topics
13 relations
Alpha 21064
Chemical vapor deposition
Chemical-mechanical planarization
Copper interconnect
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Broader (1)
Semiconductor device fabrication
Papers overview
Semantic Scholar uses AI to extract papers important to this topic.
2014
2014
Stress analyses of high spatial resolution on TSV and BEoL structures
D. Vogel
,
E. Auerswald
,
+5 authors
B. Michel
Microelectronics and reliability
2014
Corpus ID: 27956580
2012
2012
Interconnect design and analysis for Through Silicon Interposers (TSIs)
J. R. Cubillo
,
R. Weerasekera
,
+4 authors
R. Patti
IEEE International Conference on 3D System…
2012
Corpus ID: 24890169
The trend of increasing digital system performance by downscaling the device size poses daunting challenges in system design due…
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Review
2007
Review
2007
Design for millimeter-wave applications in silicon technologies
A. Cathelin
,
B. Martineau
,
+10 authors
J. Schoellkopf
European Solid-State Circuits Conference
2007
Corpus ID: 44014240
This paper presents the potentialities of advanced BiCMOS and CMOS technologies for millimeter-wave applications. To begin, the…
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2006
2006
Back-End-Of-Line Poly-Sige Disk Resonators
E. Quevy
,
Á. San Paulo
,
E. Basol
,
R. Howe
,
T. King
,
J. Bokor
19th IEEE International Conference on Micro…
2006
Corpus ID: 2669485
This paper reports the characterization of poly-silicon-germanium disk resonators at frequencies ranging from 35 to 425MHz. The…
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Review
2006
Review
2006
Cu Alloy Metallization for Self-Forming Barrier Process
J. Koike
,
M. Haneda
,
J. Iijima
,
M. Wada
International Interconnect Technology Conference
2006
Corpus ID: 8316143
A novel Cu-Mn alloy has been developed to self-form a diffusion barrier layer at metal/dielectric interface without depositing a…
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Highly Cited
2005
Highly Cited
2005
High performance 65 nm SOI technology with enhanced transistor strain and advanced-low-K BEOL
W. Lee
,
A. Waite
,
+76 authors
N. Kepler
IEEE InternationalElectron Devices Meeting…
2005
Corpus ID: 22372112
A high performance 65 nm SOI CMOS technology is presented. Dual stress liner (DSL), embedded SiGe, and stress memorization…
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Highly Cited
2004
Highly Cited
2004
Nonvolatile memory based on solid electrolytes
M. Kozicki
,
C. Gopalan
,
Muralikrishnan Balakrishnan
,
Mira Park
,
M. Mitkova
Proceedings. IEEE Computational Systems…
2004
Corpus ID: 2884270
Programmable metallization cell (PMC) memory utilizes electrochemical control of nanoscale quantities of metal in thin films of…
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2004
2004
A 0.314/spl mu/m/sup 2/ 6T-SRAM cell build with tall triple-gate devices for 45nm applications using 0.75NA 193nm lithography
A. Nackaerts
,
M. Ercken
,
+33 authors
S. Biesemans
IEDM Technical Digest. IEEE International…
2004
Corpus ID: 36543105
This paper describes the fabrication process of a fully working 6T-SRAM cell of 0.314/spl mu/m/sup 2/ build with tall triple gate…
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2002
2002
Integration of high-performance, low-leakage and mixed signal features into a 100 nm CMOS technology
T. Schafbauer
,
J. Brighten
,
+31 authors
C. Wann
Symposium on VLSI Technology. Digest of Technical…
2002
Corpus ID: 20603757
Low voltage operation in sub-0.25 /spl mu/m requirements mean that the simultaneous integration of all components on a single…
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Highly Cited
2001
Highly Cited
2001
High performance 35 nm gate length CMOS with NO oxynitride gate dielectric and ni SALICIDE
S. Inaba
,
K. Okano
,
+25 authors
H. Ishiuchi
International Electron Devices Meeting. Technical…
2001
Corpus ID: 32942393
35 nm gate length CMOS devices with oxynitride gate dielectric and Ni SALICIDE have been fabricated to study the feasibility of…
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