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FinFET-a self-aligned double-gate MOSFET scalable to 20 nm
MOSFETs with gate length down to 17 nm are reported. To suppress the short channel effect, a novel self-aligned double-gate MOSFET, FinFET, is proposed. By using boron-doped Si/sub 0.4/Ge/sub 0.6/ asExpand
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FinFET scaling to 10 nm gate length
While the selection of new "backbone" device structure in the era of post-planar CMOS is open to a few candidates, FinFET and its variants show great potential in scalability and manufacturabilityExpand
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Frequency-independent equivalent circuit model for on-chip spiral inductors
TLDR
A wide-band, physical and scalable 2-/spl Pi/ equivalent circuit model for on-chip spiral inductors is developed. Expand
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Complementary silicide source/drain thin-body MOSFETs for the 20 nm gate length regime
Thin-body transistors with silicide source/drains were fabricated with gate-lengths down to 15 nm. Complementary low-barrier silicides were used to reduce contact and series resistance. MinimumExpand
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FinFET-based SRAM design
TLDR
We show that 6-T and 4-T FinFET-based SRAM cells designed with built-in feedback achieve significant improvements in the cell static noise margin (SNM) without area penalty. Expand
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Sub-20 nm CMOS FinFET technologies
  • Y. Choi, N. Lindert, +6 authors C. Hu
  • Physics, Engineering
  • International Electron Devices Meeting. Technical…
  • 2 December 2001
A simplified fabrication process for sub-20 nm CMOS double-gate FinFETs is reported. It is a more manufacturable process and has less overlap capacitance compared to the previous FinFET (1999, 2000).Expand
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Gate length scaling and threshold voltage control of double-gate MOSFETs
In the nanoscale regime, the double-gate MOSFET can provide superior short-channel behavior. For this structure, device scaling issues are explored. Gate length scaling will be limited by the abilityExpand
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Sub-50 nm P-channel FinFET
High-performance PMOSFETs with sub-50-nm gate-length are reported. A self-aligned double-gate MOSFET structure (FinFET) is used to suppress the short-channel effects. This vertical double-gate SOIExpand
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Metal-dielectric band alignment and its implications for metal gate complementary metal-oxide-semiconductor technology
The dependence of the metal gate work function on the underlying gate dielectric in advanced metal-oxide-semiconductor (MOS) gate stacks was explored. Metal work functions on high-κ dielectrics areExpand
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SRAM Read/Write Margin Enhancements Using FinFETs
TLDR
We show that FinFET-based 6-T SRAM cells designed with pass-gate feedback (PGFB) achieve significant improvements in the cell read stability without area penalty. Expand
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